Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	611682	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

367348

1

T3

6

T5

1831

T6

938

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	521229	1			T2	1		T4	1		T5	2808
values[0x0]	228444	1			T3	13		T5	1193		T6	561
values[0x1]	229357	1			T3	9		T5	1186		T6	578

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	513482	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

465548

1

T3

7

T5

2363

T6

1209

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3179	1			T5	36		T8	1		T10	1
valid_sources[0x01]	3685	1			T5	25		T7	6		T9	2
valid_sources[0x02]	4247	1			T5	21		T7	113		T9	1
valid_sources[0x03]	3667	1			T5	18		T21	6		T89	66
valid_sources[0x04]	3191	1			T5	43		T7	155		T8	1
valid_sources[0x05]	7187	1			T5	43		T6	112		T7	1804
valid_sources[0x06]	3744	1			T5	11		T8	3		T10	4
valid_sources[0x07]	3390	1			T5	48		T9	1		T10	6
valid_sources[0x08]	3145	1			T5	19		T8	2		T10	1
valid_sources[0x09]	3407	1			T5	19		T8	2		T10	1
valid_sources[0x0a]	4442	1			T5	25		T7	197		T10	2
valid_sources[0x0b]	3694	1			T5	24		T7	112		T8	1
valid_sources[0x0c]	4040	1			T5	16		T7	579		T10	5
valid_sources[0x0d]	5350	1			T5	20		T9	2		T10	1
valid_sources[0x0e]	3665	1			T5	17		T7	224		T8	1
valid_sources[0x0f]	3235	1			T5	22		T8	2		T10	1
valid_sources[0x10]	3632	1			T5	16		T8	2		T9	1
valid_sources[0x11]	3154	1			T5	30		T10	9		T13	4
valid_sources[0x12]	3346	1			T5	19		T7	155		T10	1
valid_sources[0x13]	3477	1			T5	18		T8	1		T10	2
valid_sources[0x14]	3877	1			T5	30		T6	478		T8	5
valid_sources[0x15]	6141	1			T4	1		T5	19		T8	2
valid_sources[0x16]	3388	1			T5	29		T7	239		T8	1
valid_sources[0x17]	3253	1			T5	37		T10	1		T12	3
valid_sources[0x18]	3902	1			T5	20		T8	1		T10	7
valid_sources[0x19]	3477	1			T5	30		T6	70		T10	7
valid_sources[0x1a]	4795	1			T5	13		T9	1		T10	2
valid_sources[0x1b]	7140	1			T5	29		T6	13		T8	1
valid_sources[0x1c]	3727	1			T5	14		T9	1		T10	1
valid_sources[0x1d]	3968	1			T5	14		T8	1		T10	6
valid_sources[0x1e]	3262	1			T5	11		T8	1		T9	1
valid_sources[0x1f]	4036	1			T3	22		T5	21		T7	182
valid_sources[0x20]	3800	1			T5	12		T6	6		T7	70
valid_sources[0x21]	3129	1			T5	23		T10	4		T12	2
valid_sources[0x22]	5886	1			T5	14		T7	240		T8	3
valid_sources[0x23]	3292	1			T5	11		T8	1		T10	4
valid_sources[0x24]	3170	1			T5	25		T8	1		T21	12
valid_sources[0x25]	3967	1			T5	25		T7	70		T8	1
valid_sources[0x26]	3264	1			T5	22		T8	1		T10	1
valid_sources[0x27]	5305	1			T5	30		T8	1		T10	6
valid_sources[0x28]	3442	1			T5	15		T10	1		T21	12
valid_sources[0x29]	3731	1			T5	19		T8	2		T9	1
valid_sources[0x2a]	3029	1			T5	13		T8	4		T12	2
valid_sources[0x2b]	3457	1			T5	35		T10	1		T13	4
valid_sources[0x2c]	3066	1			T5	1		T6	7		T8	1
valid_sources[0x2d]	2877	1			T5	27		T8	3		T9	2
valid_sources[0x2e]	3346	1			T5	15		T7	7		T8	2
valid_sources[0x2f]	3458	1			T5	20		T8	3		T10	2
valid_sources[0x30]	3656	1			T5	20		T8	1		T9	2
valid_sources[0x31]	3228	1			T5	19		T8	4		T9	1
valid_sources[0x32]	3317	1			T5	44		T7	284		T8	2
valid_sources[0x33]	3665	1			T5	23		T13	3		T21	11
valid_sources[0x34]	3936	1			T5	42		T7	482		T8	2
valid_sources[0x35]	2906	1			T5	23		T12	3		T21	10
valid_sources[0x36]	3231	1			T5	19		T8	1		T9	1
valid_sources[0x37]	3669	1			T5	5		T8	1		T9	1
valid_sources[0x38]	3349	1			T5	47		T7	196		T13	3
valid_sources[0x39]	2903	1			T5	11		T8	1		T10	1
valid_sources[0x3a]	3968	1			T5	8		T6	287		T7	296
valid_sources[0x3b]	6382	1			T5	41		T6	65		T8	1
valid_sources[0x3c]	3301	1			T5	9		T10	2		T13	3
valid_sources[0x3d]	3073	1			T5	28		T8	2		T10	1
valid_sources[0x3e]	4895	1			T5	34		T7	197		T8	1
valid_sources[0x3f]	3488	1			T5	26		T7	13		T8	1
valid_sources[0x40]	4497	1			T5	18		T6	494		T8	1
valid_sources[0x41]	3936	1			T5	11		T8	1		T10	4
valid_sources[0x42]	2770	1			T5	12		T9	1		T10	2
valid_sources[0x43]	3265	1			T5	15		T7	70		T8	4
valid_sources[0x44]	3807	1			T5	20		T10	6		T12	1
valid_sources[0x45]	3862	1			T5	30		T8	1		T9	2
valid_sources[0x46]	4125	1			T5	27		T9	1		T10	3
valid_sources[0x47]	3985	1			T5	12		T7	198		T8	1
valid_sources[0x48]	4414	1			T5	28		T8	1		T10	7
valid_sources[0x49]	3919	1			T5	30		T10	15		T12	3
valid_sources[0x4a]	4330	1			T5	14		T8	2		T10	8
valid_sources[0x4b]	4483	1			T5	10		T7	155		T8	2
valid_sources[0x4c]	3197	1			T5	9		T8	2		T9	1
valid_sources[0x4d]	3913	1			T5	33		T7	721		T10	2
valid_sources[0x4e]	6691	1			T5	18		T9	1		T10	2
valid_sources[0x4f]	3597	1			T5	29		T8	1		T10	1
valid_sources[0x50]	3550	1			T5	7		T10	12		T13	2
valid_sources[0x51]	3577	1			T5	26		T8	1		T10	7
valid_sources[0x52]	3118	1			T5	18		T8	3		T10	3
valid_sources[0x53]	2928	1			T5	22		T9	1		T10	2
valid_sources[0x54]	3123	1			T5	19		T12	1		T21	16
valid_sources[0x55]	3121	1			T5	15		T8	2		T10	5
valid_sources[0x56]	3734	1			T5	15		T8	1		T9	1
valid_sources[0x57]	3676	1			T5	19		T8	1		T9	1
valid_sources[0x58]	2824	1			T5	25		T8	4		T9	1
valid_sources[0x59]	3155	1			T5	29		T7	199		T10	1
valid_sources[0x5a]	3732	1			T5	22		T8	1		T10	2
valid_sources[0x5b]	3845	1			T5	16		T8	1		T10	6
valid_sources[0x5c]	3329	1			T5	39		T21	13		T89	77
valid_sources[0x5d]	4442	1			T5	11		T6	6		T10	5
valid_sources[0x5e]	3599	1			T5	14		T10	8		T21	13
valid_sources[0x5f]	5793	1			T5	25		T8	2		T9	1
valid_sources[0x60]	3691	1			T5	21		T8	3		T9	1
valid_sources[0x61]	3922	1			T5	7		T8	1		T12	2
valid_sources[0x62]	3897	1			T5	19		T7	70		T8	1
valid_sources[0x63]	3200	1			T5	14		T12	1		T21	20
valid_sources[0x64]	3095	1			T5	5		T9	2		T10	1
valid_sources[0x65]	3343	1			T5	25		T7	113		T9	2
valid_sources[0x66]	3063	1			T5	15		T8	2		T9	1
valid_sources[0x67]	3267	1			T5	22		T7	70		T10	2
valid_sources[0x68]	3711	1			T5	24		T8	1		T9	1
valid_sources[0x69]	3240	1			T5	16		T6	1		T8	4
valid_sources[0x6a]	3986	1			T5	21		T9	1		T12	3
valid_sources[0x6b]	3422	1			T5	22		T7	168		T8	1
valid_sources[0x6c]	3158	1			T5	10		T9	3		T10	1
valid_sources[0x6d]	4198	1			T5	22		T7	323		T10	1
valid_sources[0x6e]	3546	1			T5	18		T9	3		T10	7
valid_sources[0x6f]	7015	1			T5	31		T10	7		T12	2
valid_sources[0x70]	3072	1			T5	28		T8	5		T9	1
valid_sources[0x71]	3053	1			T5	22		T7	240		T10	3
valid_sources[0x72]	3055	1			T5	10		T8	2		T9	1
valid_sources[0x73]	3086	1			T5	6		T8	7		T13	2
valid_sources[0x74]	3462	1			T5	33		T7	196		T21	7
valid_sources[0x75]	3276	1			T5	11		T8	1		T9	1
valid_sources[0x76]	3705	1			T5	26		T6	2		T8	3
valid_sources[0x77]	3331	1			T5	14		T9	3		T10	2
valid_sources[0x78]	3042	1			T5	26		T8	1		T10	6
valid_sources[0x79]	3879	1			T5	6		T8	2		T10	2
valid_sources[0x7a]	4473	1			T5	13		T7	70		T10	8
valid_sources[0x7b]	3010	1			T5	9		T8	5		T10	5
valid_sources[0x7c]	2824	1			T5	25		T8	1		T10	1
valid_sources[0x7d]	3734	1			T5	28		T7	196		T8	4
valid_sources[0x7e]	3735	1			T5	48		T6	70		T10	7
valid_sources[0x7f]	3981	1			T5	5		T7	423		T8	2
valid_sources[0x80]	3224	1			T5	19		T6	7		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

244085

1

T5

1275

T6

644

T7

4189

values[0x0]

all_enables

biggest_size

80159

1

T3

4

T5

368

T6

191

values[0x1]

all_enables

biggest_size

43104

1

T3

2

T5

188

T6

103