Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11778187	13074	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11778187	120651	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11778187	6996480	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11778187	192725	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11778187	13074	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11778187	120651	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11778187	6996480	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11778187	192725	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	13074	0	0
T5	58638	73	0	0
T6	14526	35	0	0
T7	184210	226	0	0
T8	4765	17	0	0
T9	2496	7	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	4	0	0
T13	2354	4	0	0
T21	32819	33	0	0
T22	0	4	0	0
T23	0	43	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	120651	0	0
T5	58638	682	0	0
T6	14526	325	0	0
T7	184210	2096	0	0
T8	4765	153	0	0
T9	2496	63	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	37	0	0
T13	2354	37	0	0
T21	32819	297	0	0
T22	0	37	0	0
T23	0	391	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	6996480	0	0
T1	5087	567	0	0
T2	5357	720	0	0
T3	1861	1258	0	0
T4	2438	842	0	0
T5	58638	42263	0	0
T6	14526	7047	0	0
T7	184210	137132	0	0
T8	4765	3903	0	0
T9	2496	1825	0	0
T10	3295	2669	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	192725	0	0
T5	58638	1093	0	0
T6	14526	547	0	0
T7	184210	3214	0	0
T8	4765	263	0	0
T9	2496	98	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	58	0	0
T13	2354	56	0	0
T21	32819	479	0	0
T22	0	55	0	0
T23	0	577	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	13074	0	0
T5	58638	73	0	0
T6	14526	35	0	0
T7	184210	226	0	0
T8	4765	17	0	0
T9	2496	7	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	4	0	0
T13	2354	4	0	0
T21	32819	33	0	0
T22	0	4	0	0
T23	0	43	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	120651	0	0
T5	58638	682	0	0
T6	14526	325	0	0
T7	184210	2096	0	0
T8	4765	153	0	0
T9	2496	63	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	37	0	0
T13	2354	37	0	0
T21	32819	297	0	0
T22	0	37	0	0
T23	0	391	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	6996480	0	0
T1	5087	567	0	0
T2	5357	720	0	0
T3	1861	1258	0	0
T4	2438	842	0	0
T5	58638	42263	0	0
T6	14526	7047	0	0
T7	184210	137132	0	0
T8	4765	3903	0	0
T9	2496	1825	0	0
T10	3295	2669	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	192725	0	0
T5	58638	1093	0	0
T6	14526	547	0	0
T7	184210	3214	0	0
T8	4765	263	0	0
T9	2496	98	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	58	0	0
T13	2354	56	0	0
T21	32819	479	0	0
T22	0	55	0	0
T23	0	577	0	0