Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55409301	8909	0	0
CascadeEffAonToRstPorAboveRise_A	55409301	8909	0	0
CascadeEffAonToRstPorIoAboveFall_A	53190885	8909	0	0
CascadeEffAonToRstPorIoAboveRise_A	53190885	8909	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26596212	8909	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26596212	8909	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13297887	8909	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13297887	8909	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26596244	8909	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26596244	8909	0	0
CascadeLcToLcAboveFall_A	55409301	21983	0	0
CascadeLcToLcAboveRise_A	55409301	21983	0	0
CascadeLcToLcAonAboveFall_A	1678653	21983	0	0
CascadeLcToLcAonAboveRise_A	1678653	21983	0	0
CascadeLcToLcShadowedAboveFall_A	55409301	21983	0	0
CascadeLcToLcShadowedAboveRise_A	55409301	21983	0	0
CascadePorToAonAboveFall_A	1678653	7101	0	0
CascadeSysToSysAboveFall_A	55409301	21983	0	0
CascadeSysToSysAboveRise_A	55409301	21983	0	0
ScanRstToAonRise_A	1678653	220	0	0
StablePorToAonRise_A	1678653	8909	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11778187	21983	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11778187	21983	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11778187	21983	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11778187	21983	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13297887	21983	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13297887	21983	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11778187	21983	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11778187	21983	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11778187	21983	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11778187	21983	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55409301	8909	0	0
T1	24270	8	0	0
T2	23002	2	0	0
T3	8034	1	0	0
T4	10638	2	0	0
T5	280642	32	0	0
T6	79018	16	0	0
T7	875527	103	0	0
T8	24060	1	0	0
T9	12547	1	0	0
T10	13910	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55409301	8909	0	0
T1	24270	8	0	0
T2	23002	2	0	0
T3	8034	1	0	0
T4	10638	2	0	0
T5	280642	32	0	0
T6	79018	16	0	0
T7	875527	103	0	0
T8	24060	1	0	0
T9	12547	1	0	0
T10	13910	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53190885	8909	0	0
T1	23299	8	0	0
T2	22081	2	0	0
T3	7713	1	0	0
T4	10213	2	0	0
T5	269420	32	0	0
T6	75825	16	0	0
T7	840437	103	0	0
T8	23096	1	0	0
T9	12044	1	0	0
T10	13354	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53190885	8909	0	0
T1	23299	8	0	0
T2	22081	2	0	0
T3	7713	1	0	0
T4	10213	2	0	0
T5	269420	32	0	0
T6	75825	16	0	0
T7	840437	103	0	0
T8	23096	1	0	0
T9	12044	1	0	0
T10	13354	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596212	8909	0	0
T1	11645	8	0	0
T2	11040	2	0	0
T3	3856	1	0	0
T4	5106	2	0	0
T5	134710	32	0	0
T6	37925	16	0	0
T7	420259	103	0	0
T8	11547	1	0	0
T9	6021	1	0	0
T10	6677	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596212	8909	0	0
T1	11645	8	0	0
T2	11040	2	0	0
T3	3856	1	0	0
T4	5106	2	0	0
T5	134710	32	0	0
T6	37925	16	0	0
T7	420259	103	0	0
T8	11547	1	0	0
T9	6021	1	0	0
T10	6677	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	8909	0	0
T1	5823	8	0	0
T2	5519	2	0	0
T3	1927	1	0	0
T4	2552	2	0	0
T5	67365	32	0	0
T6	18958	16	0	0
T7	210121	103	0	0
T8	5773	1	0	0
T9	3010	1	0	0
T10	3337	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	8909	0	0
T1	5823	8	0	0
T2	5519	2	0	0
T3	1927	1	0	0
T4	2552	2	0	0
T5	67365	32	0	0
T6	18958	16	0	0
T7	210121	103	0	0
T8	5773	1	0	0
T9	3010	1	0	0
T10	3337	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596244	8909	0	0
T1	11648	8	0	0
T2	11040	2	0	0
T3	3856	1	0	0
T4	5105	2	0	0
T5	134717	32	0	0
T6	37913	16	0	0
T7	420252	103	0	0
T8	11548	1	0	0
T9	6021	1	0	0
T10	6677	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596244	8909	0	0
T1	11648	8	0	0
T2	11040	2	0	0
T3	3856	1	0	0
T4	5105	2	0	0
T5	134717	32	0	0
T6	37913	16	0	0
T7	420252	103	0	0
T8	11548	1	0	0
T9	6021	1	0	0
T10	6677	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55409301	21983	0	0
T1	24270	8	0	0
T2	23002	2	0	0
T3	8034	1	0	0
T4	10638	2	0	0
T5	280642	105	0	0
T6	79018	51	0	0
T7	875527	329	0	0
T8	24060	18	0	0
T9	12547	8	0	0
T10	13910	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55409301	21983	0	0
T1	24270	8	0	0
T2	23002	2	0	0
T3	8034	1	0	0
T4	10638	2	0	0
T5	280642	105	0	0
T6	79018	51	0	0
T7	875527	329	0	0
T8	24060	18	0	0
T9	12547	8	0	0
T10	13910	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1678653	21983	0	0
T1	729	8	0	0
T2	690	2	0	0
T3	239	1	0	0
T4	317	2	0	0
T5	8593	105	0	0
T6	2451	51	0	0
T7	26649	329	0	0
T8	720	18	0	0
T9	375	8	0	0
T10	415	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1678653	21983	0	0
T1	729	8	0	0
T2	690	2	0	0
T3	239	1	0	0
T4	317	2	0	0
T5	8593	105	0	0
T6	2451	51	0	0
T7	26649	329	0	0
T8	720	18	0	0
T9	375	8	0	0
T10	415	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55409301	21983	0	0
T1	24270	8	0	0
T2	23002	2	0	0
T3	8034	1	0	0
T4	10638	2	0	0
T5	280642	105	0	0
T6	79018	51	0	0
T7	875527	329	0	0
T8	24060	18	0	0
T9	12547	8	0	0
T10	13910	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55409301	21983	0	0
T1	24270	8	0	0
T2	23002	2	0	0
T3	8034	1	0	0
T4	10638	2	0	0
T5	280642	105	0	0
T6	79018	51	0	0
T7	875527	329	0	0
T8	24060	18	0	0
T9	12547	8	0	0
T10	13910	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1678653	7101	0	0
T1	729	8	0	0
T2	690	21	0	0
T3	239	1	0	0
T4	317	5	0	0
T5	8593	23	0	0
T6	2451	8	0	0
T7	26649	49	0	0
T8	720	1	0	0
T9	375	1	0	0
T10	415	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55409301	21983	0	0
T1	24270	8	0	0
T2	23002	2	0	0
T3	8034	1	0	0
T4	10638	2	0	0
T5	280642	105	0	0
T6	79018	51	0	0
T7	875527	329	0	0
T8	24060	18	0	0
T9	12547	8	0	0
T10	13910	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55409301	21983	0	0
T1	24270	8	0	0
T2	23002	2	0	0
T3	8034	1	0	0
T4	10638	2	0	0
T5	280642	105	0	0
T6	79018	51	0	0
T7	875527	329	0	0
T8	24060	18	0	0
T9	12547	8	0	0
T10	13910	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1678653	220	0	0
T5	8593	4	0	0
T6	2451	1	0	0
T7	26649	6	0	0
T8	720	0	0	0
T9	375	0	0	0
T10	415	0	0	0
T11	623	0	0	0
T12	507	1	0	0
T13	324	0	0	0
T21	4895	2	0	0
T23	0	2	0	0
T89	0	2	0	0
T109	0	1	0	0
T111	0	1	0	0
T145	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1678653	8909	0	0
T1	729	8	0	0
T2	690	2	0	0
T3	239	1	0	0
T4	317	2	0	0
T5	8593	32	0	0
T6	2451	16	0	0
T7	26649	103	0	0
T8	720	1	0	0
T9	375	1	0	0
T10	415	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	21983	0	0
T1	5087	8	0	0
T2	5357	2	0	0
T3	1861	1	0	0
T4	2438	2	0	0
T5	58638	105	0	0
T6	14526	51	0	0
T7	184210	329	0	0
T8	4765	18	0	0
T9	2496	8	0	0
T10	3295	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	21983	0	0
T1	5087	8	0	0
T2	5357	2	0	0
T3	1861	1	0	0
T4	2438	2	0	0
T5	58638	105	0	0
T6	14526	51	0	0
T7	184210	329	0	0
T8	4765	18	0	0
T9	2496	8	0	0
T10	3295	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	21983	0	0
T1	5087	8	0	0
T2	5357	2	0	0
T3	1861	1	0	0
T4	2438	2	0	0
T5	58638	105	0	0
T6	14526	51	0	0
T7	184210	329	0	0
T8	4765	18	0	0
T9	2496	8	0	0
T10	3295	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	21983	0	0
T1	5087	8	0	0
T2	5357	2	0	0
T3	1861	1	0	0
T4	2438	2	0	0
T5	58638	105	0	0
T6	14526	51	0	0
T7	184210	329	0	0
T8	4765	18	0	0
T9	2496	8	0	0
T10	3295	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	21983	0	0
T1	5823	8	0	0
T2	5519	2	0	0
T3	1927	1	0	0
T4	2552	2	0	0
T5	67365	105	0	0
T6	18958	51	0	0
T7	210121	329	0	0
T8	5773	18	0	0
T9	3010	8	0	0
T10	3337	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	21983	0	0
T1	5823	8	0	0
T2	5519	2	0	0
T3	1927	1	0	0
T4	2552	2	0	0
T5	67365	105	0	0
T6	18958	51	0	0
T7	210121	329	0	0
T8	5773	18	0	0
T9	3010	8	0	0
T10	3337	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	21983	0	0
T1	5087	8	0	0
T2	5357	2	0	0
T3	1861	1	0	0
T4	2438	2	0	0
T5	58638	105	0	0
T6	14526	51	0	0
T7	184210	329	0	0
T8	4765	18	0	0
T9	2496	8	0	0
T10	3295	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	21983	0	0
T1	5087	8	0	0
T2	5357	2	0	0
T3	1861	1	0	0
T4	2438	2	0	0
T5	58638	105	0	0
T6	14526	51	0	0
T7	184210	329	0	0
T8	4765	18	0	0
T9	2496	8	0	0
T10	3295	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	21983	0	0
T1	5087	8	0	0
T2	5357	2	0	0
T3	1861	1	0	0
T4	2438	2	0	0
T5	58638	105	0	0
T6	14526	51	0	0
T7	184210	329	0	0
T8	4765	18	0	0
T9	2496	8	0	0
T10	3295	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11778187	21983	0	0
T1	5087	8	0	0
T2	5357	2	0	0
T3	1861	1	0	0
T4	2438	2	0	0
T5	58638	105	0	0
T6	14526	51	0	0
T7	184210	329	0	0
T8	4765	18	0	0
T9	2496	8	0	0
T10	3295	1	0	0