Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T10
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13297887	13938	0	0
gen_assertions[0].RstEnOn_A	13297887	1040	0	0
gen_assertions[0].RstNOff_A	13297887	13938	0	0
gen_assertions[0].RstNOn_A	13297887	1040	0	0
gen_assertions[1].RstEnOff_A	53190885	12699	0	0
gen_assertions[1].RstEnOn_A	53190885	978	0	0
gen_assertions[1].RstNOff_A	53190885	12699	0	0
gen_assertions[1].RstNOn_A	53190885	978	0	0
gen_assertions[2].RstEnOff_A	26596212	12756	0	0
gen_assertions[2].RstEnOn_A	26596212	999	0	0
gen_assertions[2].RstNOff_A	26596212	12756	0	0
gen_assertions[2].RstNOn_A	26596212	999	0	0
gen_assertions[3].RstEnOff_A	26596244	12805	0	0
gen_assertions[3].RstEnOn_A	26596244	1041	0	0
gen_assertions[3].RstNOff_A	26596244	12805	0	0
gen_assertions[3].RstNOn_A	26596244	1041	0	0
gen_assertions[4].RstEnOff_A	1678653	21786	0	0
gen_assertions[4].RstEnOn_A	1678653	1103	0	0
gen_assertions[4].RstNOff_A	1678653	21786	0	0
gen_assertions[4].RstNOn_A	1678653	1103	0	0
gen_assertions[5].RstEnOff_A	13297887	14195	0	0
gen_assertions[5].RstEnOn_A	13297887	1157	0	0
gen_assertions[5].RstNOff_A	13297887	14195	0	0
gen_assertions[5].RstNOn_A	13297887	1157	0	0
gen_assertions[6].RstEnOff_A	13297887	14232	0	0
gen_assertions[6].RstEnOn_A	13297887	1193	0	0
gen_assertions[6].RstNOff_A	13297887	14232	0	0
gen_assertions[6].RstNOn_A	13297887	1193	0	0
gen_assertions[7].RstEnOff_A	13297887	14283	0	0
gen_assertions[7].RstEnOn_A	13297887	1244	0	0
gen_assertions[7].RstNOff_A	13297887	14283	0	0
gen_assertions[7].RstNOn_A	13297887	1244	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	13938	0	0
T5	67365	75	0	0
T6	18958	35	0	0
T7	210121	241	0	0
T8	5773	17	0	0
T9	3010	7	0	0
T10	3337	5	0	0
T11	4996	0	0	0
T12	4069	4	0	0
T13	2595	4	0	0
T21	38706	33	0	0
T22	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	1040	0	0
T5	67365	2	0	0
T6	18958	0	0	0
T7	210121	16	0	0
T8	5773	4	0	0
T9	3010	1	0	0
T10	3337	5	0	0
T11	4996	0	0	0
T12	4069	0	0	0
T13	2595	0	0	0
T21	38706	0	0	0
T61	0	3	0	0
T62	0	1	0	0
T89	0	25	0	0
T91	0	7	0	0
T92	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	13938	0	0
T5	67365	75	0	0
T6	18958	35	0	0
T7	210121	241	0	0
T8	5773	17	0	0
T9	3010	7	0	0
T10	3337	5	0	0
T11	4996	0	0	0
T12	4069	4	0	0
T13	2595	4	0	0
T21	38706	33	0	0
T22	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	1040	0	0
T5	67365	2	0	0
T6	18958	0	0	0
T7	210121	16	0	0
T8	5773	4	0	0
T9	3010	1	0	0
T10	3337	5	0	0
T11	4996	0	0	0
T12	4069	0	0	0
T13	2595	0	0	0
T21	38706	0	0	0
T61	0	3	0	0
T62	0	1	0	0
T89	0	25	0	0
T91	0	7	0	0
T92	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53190885	12699	0	0
T5	269420	71	0	0
T6	75825	35	0	0
T7	840437	206	0	0
T8	23096	14	0	0
T9	12044	5	0	0
T10	13354	6	0	0
T11	19991	0	0	0
T12	16275	4	0	0
T13	10394	4	0	0
T21	154840	30	0	0
T22	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53190885	978	0	0
T5	269420	4	0	0
T6	75825	0	0	0
T7	840437	15	0	0
T8	23096	0	0	0
T9	12044	0	0	0
T10	13354	6	0	0
T11	19991	0	0	0
T12	16275	0	0	0
T13	10394	0	0	0
T21	154840	0	0	0
T39	0	1	0	0
T49	0	3	0	0
T53	0	5	0	0
T61	0	3	0	0
T69	0	1	0	0
T89	0	22	0	0
T91	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53190885	12699	0	0
T5	269420	71	0	0
T6	75825	35	0	0
T7	840437	206	0	0
T8	23096	14	0	0
T9	12044	5	0	0
T10	13354	6	0	0
T11	19991	0	0	0
T12	16275	4	0	0
T13	10394	4	0	0
T21	154840	30	0	0
T22	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53190885	978	0	0
T5	269420	4	0	0
T6	75825	0	0	0
T7	840437	15	0	0
T8	23096	0	0	0
T9	12044	0	0	0
T10	13354	6	0	0
T11	19991	0	0	0
T12	16275	0	0	0
T13	10394	0	0	0
T21	154840	0	0	0
T39	0	1	0	0
T49	0	3	0	0
T53	0	5	0	0
T61	0	3	0	0
T69	0	1	0	0
T89	0	22	0	0
T91	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596212	12756	0	0
T5	134710	71	0	0
T6	37925	35	0	0
T7	420259	204	0	0
T8	11547	14	0	0
T9	6021	5	0	0
T10	6677	6	0	0
T11	9995	0	0	0
T12	8141	4	0	0
T13	5196	4	0	0
T21	77411	30	0	0
T22	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596212	999	0	0
T5	134710	4	0	0
T6	37925	0	0	0
T7	420259	14	0	0
T8	11547	0	0	0
T9	6021	0	0	0
T10	6677	6	0	0
T11	9995	0	0	0
T12	8141	0	0	0
T13	5196	0	0	0
T21	77411	0	0	0
T34	0	1	0	0
T49	0	5	0	0
T53	0	5	0	0
T61	0	4	0	0
T62	0	1	0	0
T89	0	24	0	0
T93	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596212	12756	0	0
T5	134710	71	0	0
T6	37925	35	0	0
T7	420259	204	0	0
T8	11547	14	0	0
T9	6021	5	0	0
T10	6677	6	0	0
T11	9995	0	0	0
T12	8141	4	0	0
T13	5196	4	0	0
T21	77411	30	0	0
T22	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596212	999	0	0
T5	134710	4	0	0
T6	37925	0	0	0
T7	420259	14	0	0
T8	11547	0	0	0
T9	6021	0	0	0
T10	6677	6	0	0
T11	9995	0	0	0
T12	8141	0	0	0
T13	5196	0	0	0
T21	77411	0	0	0
T34	0	1	0	0
T49	0	5	0	0
T53	0	5	0	0
T61	0	4	0	0
T62	0	1	0	0
T89	0	24	0	0
T93	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596244	12805	0	0
T5	134717	71	0	0
T6	37913	35	0	0
T7	420252	206	0	0
T8	11548	14	0	0
T9	6021	5	0	0
T10	6677	7	0	0
T11	9995	0	0	0
T12	8140	4	0	0
T13	5194	4	0	0
T21	77422	30	0	0
T22	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596244	1041	0	0
T5	134717	4	0	0
T6	37913	0	0	0
T7	420252	16	0	0
T8	11548	0	0	0
T9	6021	0	0	0
T10	6677	7	0	0
T11	9995	0	0	0
T12	8140	0	0	0
T13	5194	0	0	0
T21	77422	0	0	0
T49	0	7	0	0
T53	0	6	0	0
T61	0	6	0	0
T89	0	21	0	0
T93	0	5	0	0
T94	0	1	0	0
T95	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596244	12805	0	0
T5	134717	71	0	0
T6	37913	35	0	0
T7	420252	206	0	0
T8	11548	14	0	0
T9	6021	5	0	0
T10	6677	7	0	0
T11	9995	0	0	0
T12	8140	4	0	0
T13	5194	4	0	0
T21	77422	30	0	0
T22	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26596244	1041	0	0
T5	134717	4	0	0
T6	37913	0	0	0
T7	420252	16	0	0
T8	11548	0	0	0
T9	6021	0	0	0
T10	6677	7	0	0
T11	9995	0	0	0
T12	8140	0	0	0
T13	5194	0	0	0
T21	77422	0	0	0
T49	0	7	0	0
T53	0	6	0	0
T61	0	6	0	0
T89	0	21	0	0
T93	0	5	0	0
T94	0	1	0	0
T95	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1678653	21786	0	0
T1	729	3	0	0
T2	690	2	0	0
T3	239	1	0	0
T4	317	2	0	0
T5	8593	108	0	0
T6	2451	51	0	0
T7	26649	338	0	0
T8	720	17	0	0
T9	375	7	0	0
T10	415	9	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1678653	1103	0	0
T5	8593	4	0	0
T6	2451	0	0	0
T7	26649	17	0	0
T8	720	0	0	0
T9	375	0	0	0
T10	415	8	0	0
T11	623	0	0	0
T12	507	0	0	0
T13	324	0	0	0
T21	4895	0	0	0
T37	0	1	0	0
T49	0	7	0	0
T53	0	8	0	0
T61	0	7	0	0
T62	0	1	0	0
T89	0	24	0	0
T94	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1678653	21786	0	0
T1	729	3	0	0
T2	690	2	0	0
T3	239	1	0	0
T4	317	2	0	0
T5	8593	108	0	0
T6	2451	51	0	0
T7	26649	338	0	0
T8	720	17	0	0
T9	375	7	0	0
T10	415	9	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1678653	1103	0	0
T5	8593	4	0	0
T6	2451	0	0	0
T7	26649	17	0	0
T8	720	0	0	0
T9	375	0	0	0
T10	415	8	0	0
T11	623	0	0	0
T12	507	0	0	0
T13	324	0	0	0
T21	4895	0	0	0
T37	0	1	0	0
T49	0	7	0	0
T53	0	8	0	0
T61	0	7	0	0
T62	0	1	0	0
T89	0	24	0	0
T94	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	14195	0	0
T5	67365	77	0	0
T6	18958	35	0	0
T7	210121	240	0	0
T8	5773	17	0	0
T9	3010	7	0	0
T10	3337	9	0	0
T11	4996	0	0	0
T12	4069	4	0	0
T13	2595	4	0	0
T21	38706	33	0	0
T22	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	1157	0	0
T5	67365	4	0	0
T6	18958	0	0	0
T7	210121	15	0	0
T8	5773	0	0	0
T9	3010	0	0	0
T10	3337	9	0	0
T11	4996	0	0	0
T12	4069	0	0	0
T13	2595	0	0	0
T21	38706	0	0	0
T49	0	9	0	0
T53	0	9	0	0
T61	0	8	0	0
T69	0	1	0	0
T89	0	24	0	0
T93	0	8	0	0
T94	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	14195	0	0
T5	67365	77	0	0
T6	18958	35	0	0
T7	210121	240	0	0
T8	5773	17	0	0
T9	3010	7	0	0
T10	3337	9	0	0
T11	4996	0	0	0
T12	4069	4	0	0
T13	2595	4	0	0
T21	38706	33	0	0
T22	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	1157	0	0
T5	67365	4	0	0
T6	18958	0	0	0
T7	210121	15	0	0
T8	5773	0	0	0
T9	3010	0	0	0
T10	3337	9	0	0
T11	4996	0	0	0
T12	4069	0	0	0
T13	2595	0	0	0
T21	38706	0	0	0
T49	0	9	0	0
T53	0	9	0	0
T61	0	8	0	0
T69	0	1	0	0
T89	0	24	0	0
T93	0	8	0	0
T94	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	14232	0	0
T5	67365	78	0	0
T6	18958	35	0	0
T7	210121	238	0	0
T8	5773	17	0	0
T9	3010	7	0	0
T10	3337	9	0	0
T11	4996	0	0	0
T12	4069	4	0	0
T13	2595	4	0	0
T21	38706	33	0	0
T22	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	1193	0	0
T5	67365	5	0	0
T6	18958	0	0	0
T7	210121	13	0	0
T8	5773	0	0	0
T9	3010	0	0	0
T10	3337	9	0	0
T11	4996	0	0	0
T12	4069	0	0	0
T13	2595	0	0	0
T21	38706	0	0	0
T49	0	8	0	0
T50	0	1	0	0
T53	0	10	0	0
T61	0	9	0	0
T62	0	1	0	0
T89	0	24	0	0
T96	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	14232	0	0
T5	67365	78	0	0
T6	18958	35	0	0
T7	210121	238	0	0
T8	5773	17	0	0
T9	3010	7	0	0
T10	3337	9	0	0
T11	4996	0	0	0
T12	4069	4	0	0
T13	2595	4	0	0
T21	38706	33	0	0
T22	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	1193	0	0
T5	67365	5	0	0
T6	18958	0	0	0
T7	210121	13	0	0
T8	5773	0	0	0
T9	3010	0	0	0
T10	3337	9	0	0
T11	4996	0	0	0
T12	4069	0	0	0
T13	2595	0	0	0
T21	38706	0	0	0
T49	0	8	0	0
T50	0	1	0	0
T53	0	10	0	0
T61	0	9	0	0
T62	0	1	0	0
T89	0	24	0	0
T96	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	14283	0	0
T5	67365	74	0	0
T6	18958	35	0	0
T7	210121	242	0	0
T8	5773	17	0	0
T9	3010	7	0	0
T10	3337	11	0	0
T11	4996	0	0	0
T12	4069	4	0	0
T13	2595	4	0	0
T21	38706	33	0	0
T22	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	1244	0	0
T5	67365	1	0	0
T6	18958	0	0	0
T7	210121	18	0	0
T8	5773	0	0	0
T9	3010	0	0	0
T10	3337	11	0	0
T11	4996	0	0	0
T12	4069	0	0	0
T13	2595	0	0	0
T21	38706	0	0	0
T39	0	1	0	0
T49	0	10	0	0
T53	0	10	0	0
T61	0	10	0	0
T89	0	24	0	0
T93	0	10	0	0
T94	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	14283	0	0
T5	67365	74	0	0
T6	18958	35	0	0
T7	210121	242	0	0
T8	5773	17	0	0
T9	3010	7	0	0
T10	3337	11	0	0
T11	4996	0	0	0
T12	4069	4	0	0
T13	2595	4	0	0
T21	38706	33	0	0
T22	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13297887	1244	0	0
T5	67365	1	0	0
T6	18958	0	0	0
T7	210121	18	0	0
T8	5773	0	0	0
T9	3010	0	0	0
T10	3337	11	0	0
T11	4996	0	0	0
T12	4069	0	0	0
T13	2595	0	0	0
T21	38706	0	0	0
T39	0	1	0	0
T49	0	10	0	0
T53	0	10	0	0
T61	0	10	0	0
T89	0	24	0	0
T93	0	10	0	0
T94	0	1	0	0