Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12527472	7566	0	0
alert_regwen_rd_A	12527472	5478	0	0
cpu_regwen_rd_A	12527472	5188	0	0
sw_rst_ctrl_n_0_rd_A	12527472	9957	0	0
sw_rst_ctrl_n_1_rd_A	12527472	9727	0	0
sw_rst_ctrl_n_2_rd_A	12527472	9851	0	0
sw_rst_ctrl_n_3_rd_A	12527472	9742	0	0
sw_rst_ctrl_n_4_rd_A	12527472	9692	0	0
sw_rst_ctrl_n_5_rd_A	12527472	9864	0	0
sw_rst_ctrl_n_6_rd_A	12527472	10019	0	0
sw_rst_ctrl_n_7_rd_A	12527472	9777	0	0
sw_rst_regwen_0_rd_A	12527472	5946	0	0
sw_rst_regwen_1_rd_A	12527472	5834	0	0
sw_rst_regwen_2_rd_A	12527472	5977	0	0
sw_rst_regwen_3_rd_A	12527472	5923	0	0
sw_rst_regwen_4_rd_A	12527472	6052	0	0
sw_rst_regwen_5_rd_A	12527472	5821	0	0
sw_rst_regwen_6_rd_A	12527472	5821	0	0
sw_rst_regwen_7_rd_A	12527472	6080	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	7566	0	0
T65	3068	18	0	0
T66	2466	13	0	0
T70	4524	510	0	0
T71	22508	2	0	0
T72	4087	559	0	0
T98	2406	6	0	0
T100	2823	6	0	0
T102	21614	3	0	0
T103	2339	15	0	0
T135	14452	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	5478	0	0
T23	39588	34	0	0
T61	9704	0	0	0
T77	1942	0	0	0
T89	95948	0	0	0
T90	2092	0	0	0
T109	37806	45	0	0
T110	33592	54	0	0
T111	30514	59	0	0
T114	0	31	0	0
T115	1949	0	0	0
T116	1492	0	0	0
T118	0	319	0	0
T122	0	435	0	0
T124	0	63	0	0
T125	0	66	0	0
T144	0	72	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	5188	0	0
T23	39588	25	0	0
T61	9704	0	0	0
T77	1942	0	0	0
T89	95948	0	0	0
T90	2092	0	0	0
T109	37806	22	0	0
T110	33592	51	0	0
T111	30514	64	0	0
T114	0	28	0	0
T115	1949	0	0	0
T116	1492	0	0	0
T118	0	309	0	0
T122	0	403	0	0
T124	0	58	0	0
T125	0	54	0	0
T144	0	66	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	9957	0	0
T8	4765	37	0	0
T9	2496	0	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	0	0	0
T13	2354	0	0	0
T21	32819	0	0	0
T22	3708	0	0	0
T23	0	33	0	0
T46	0	37	0	0
T49	0	175	0	0
T53	0	170	0	0
T55	1712	0	0	0
T61	0	112	0	0
T73	5091	0	0	0
T92	0	10	0	0
T109	0	24	0	0
T110	0	49	0	0
T111	0	45	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	9727	0	0
T8	4765	34	0	0
T9	2496	0	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	0	0	0
T13	2354	0	0	0
T21	32819	0	0	0
T22	3708	0	0	0
T23	0	58	0	0
T46	0	36	0	0
T49	0	119	0	0
T53	0	172	0	0
T55	1712	0	0	0
T61	0	132	0	0
T73	5091	0	0	0
T92	0	27	0	0
T109	0	28	0	0
T110	0	56	0	0
T111	0	51	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	9851	0	0
T8	4765	44	0	0
T9	2496	0	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	0	0	0
T13	2354	0	0	0
T21	32819	0	0	0
T22	3708	0	0	0
T23	0	19	0	0
T46	0	37	0	0
T49	0	145	0	0
T53	0	171	0	0
T55	1712	0	0	0
T61	0	157	0	0
T73	5091	0	0	0
T92	0	19	0	0
T109	0	26	0	0
T110	0	58	0	0
T111	0	35	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	9742	0	0
T8	4765	33	0	0
T9	2496	0	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	0	0	0
T13	2354	0	0	0
T21	32819	0	0	0
T22	3708	0	0	0
T23	0	22	0	0
T46	0	23	0	0
T49	0	145	0	0
T53	0	171	0	0
T55	1712	0	0	0
T61	0	132	0	0
T73	5091	0	0	0
T92	0	22	0	0
T109	0	30	0	0
T110	0	42	0	0
T111	0	64	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	9692	0	0
T8	4765	37	0	0
T9	2496	0	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	0	0	0
T13	2354	0	0	0
T21	32819	0	0	0
T22	3708	0	0	0
T23	0	39	0	0
T46	0	27	0	0
T49	0	171	0	0
T53	0	152	0	0
T55	1712	0	0	0
T61	0	146	0	0
T73	5091	0	0	0
T92	0	19	0	0
T109	0	29	0	0
T110	0	42	0	0
T111	0	63	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	9864	0	0
T8	4765	32	0	0
T9	2496	0	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	0	0	0
T13	2354	0	0	0
T21	32819	0	0	0
T22	3708	0	0	0
T23	0	33	0	0
T46	0	17	0	0
T49	0	164	0	0
T53	0	133	0	0
T55	1712	0	0	0
T61	0	133	0	0
T73	5091	0	0	0
T92	0	16	0	0
T109	0	30	0	0
T110	0	40	0	0
T111	0	29	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	10019	0	0
T8	4765	36	0	0
T9	2496	0	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	0	0	0
T13	2354	0	0	0
T21	32819	0	0	0
T22	3708	0	0	0
T23	0	38	0	0
T46	0	34	0	0
T49	0	143	0	0
T53	0	169	0	0
T55	1712	0	0	0
T61	0	167	0	0
T73	5091	0	0	0
T92	0	26	0	0
T109	0	27	0	0
T110	0	52	0	0
T111	0	57	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	9777	0	0
T8	4765	22	0	0
T9	2496	0	0	0
T10	3295	0	0	0
T11	4834	0	0	0
T12	3779	0	0	0
T13	2354	0	0	0
T21	32819	0	0	0
T22	3708	0	0	0
T23	0	38	0	0
T46	0	21	0	0
T49	0	147	0	0
T53	0	172	0	0
T55	1712	0	0	0
T61	0	132	0	0
T73	5091	0	0	0
T92	0	25	0	0
T109	0	43	0	0
T110	0	63	0	0
T111	0	50	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	5946	0	0
T23	39588	60	0	0
T34	0	1	0	0
T49	0	30	0	0
T53	0	44	0	0
T61	9704	29	0	0
T77	1942	0	0	0
T89	95948	0	0	0
T90	2092	0	0	0
T95	0	14	0	0
T96	0	9	0	0
T109	37806	28	0	0
T110	33592	44	0	0
T111	30514	59	0	0
T115	1949	0	0	0
T116	1492	0	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	5834	0	0
T23	39588	30	0	0
T34	0	5	0	0
T49	0	31	0	0
T53	0	32	0	0
T61	9704	39	0	0
T77	1942	0	0	0
T89	95948	0	0	0
T90	2092	0	0	0
T95	0	1	0	0
T96	0	12	0	0
T109	37806	16	0	0
T110	33592	50	0	0
T111	30514	57	0	0
T115	1949	0	0	0
T116	1492	0	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	5977	0	0
T23	39588	37	0	0
T34	0	19	0	0
T49	0	38	0	0
T53	0	38	0	0
T61	9704	45	0	0
T77	1942	0	0	0
T89	95948	0	0	0
T90	2092	0	0	0
T95	0	6	0	0
T109	37806	27	0	0
T110	33592	54	0	0
T111	30514	43	0	0
T114	0	33	0	0
T115	1949	0	0	0
T116	1492	0	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	5923	0	0
T23	39588	42	0	0
T34	0	2	0	0
T49	0	34	0	0
T53	0	36	0	0
T61	9704	35	0	0
T77	1942	0	0	0
T89	95948	0	0	0
T90	2092	0	0	0
T95	0	4	0	0
T96	0	4	0	0
T109	37806	47	0	0
T110	33592	60	0	0
T111	30514	54	0	0
T115	1949	0	0	0
T116	1492	0	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	6052	0	0
T23	39588	30	0	0
T34	0	8	0	0
T49	0	27	0	0
T53	0	48	0	0
T61	9704	32	0	0
T77	1942	0	0	0
T89	95948	0	0	0
T90	2092	0	0	0
T95	0	5	0	0
T96	0	5	0	0
T109	37806	40	0	0
T110	33592	45	0	0
T111	30514	47	0	0
T115	1949	0	0	0
T116	1492	0	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	5821	0	0
T23	39588	35	0	0
T34	0	10	0	0
T49	0	21	0	0
T53	0	29	0	0
T61	9704	33	0	0
T77	1942	0	0	0
T89	95948	0	0	0
T90	2092	0	0	0
T95	0	10	0	0
T96	0	10	0	0
T109	37806	47	0	0
T110	33592	51	0	0
T111	30514	43	0	0
T115	1949	0	0	0
T116	1492	0	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	5821	0	0
T23	39588	22	0	0
T34	0	7	0	0
T49	0	26	0	0
T53	0	27	0	0
T61	9704	37	0	0
T77	1942	0	0	0
T89	95948	0	0	0
T90	2092	0	0	0
T95	0	8	0	0
T96	0	6	0	0
T109	37806	36	0	0
T110	33592	47	0	0
T111	30514	57	0	0
T115	1949	0	0	0
T116	1492	0	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12527472	6080	0	0
T23	39588	47	0	0
T34	0	4	0	0
T49	0	28	0	0
T53	0	44	0	0
T61	9704	35	0	0
T77	1942	0	0	0
T89	95948	0	0	0
T90	2092	0	0	0
T95	0	1	0	0
T96	0	10	0	0
T109	37806	29	0	0
T110	33592	44	0	0
T111	30514	44	0	0
T115	1949	0	0	0
T116	1492	0	0	0