Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	628877	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

374525

1

T1

9

T2

309

T4

1077

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	535371	1			T1	9		T2	427		T3	20
values[0x0]	233922	1			T1	5		T2	212		T4	823
values[0x1]	234109	1			T1	6		T2	169		T4	877

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	527793	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

475609

1

T1

9

T2

378

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3479	1			T1	1		T2	4		T5	12
valid_sources[0x01]	3800	1			T2	2		T5	11		T6	1
valid_sources[0x02]	3628	1			T2	1		T5	26		T6	1
valid_sources[0x03]	5003	1			T2	3		T5	15		T13	2
valid_sources[0x04]	3711	1			T5	9		T6	1		T7	12
valid_sources[0x05]	6749	1			T1	3		T2	5		T5	10
valid_sources[0x06]	5376	1			T2	2		T5	12		T6	1
valid_sources[0x07]	3067	1			T2	3		T5	10		T7	3
valid_sources[0x08]	4080	1			T2	3		T5	14		T6	1
valid_sources[0x09]	3992	1			T2	4		T5	10		T7	10
valid_sources[0x0a]	3545	1			T2	4		T5	11		T14	28
valid_sources[0x0b]	6564	1			T2	7		T5	10		T6	3
valid_sources[0x0c]	3808	1			T2	7		T5	9		T15	3
valid_sources[0x0d]	3493	1			T2	1		T5	19		T54	2
valid_sources[0x0e]	3666	1			T2	5		T5	15		T7	4
valid_sources[0x0f]	3595	1			T2	3		T5	12		T13	3
valid_sources[0x10]	3123	1			T2	3		T5	10		T6	1
valid_sources[0x11]	4227	1			T2	3		T5	19		T6	3
valid_sources[0x12]	3348	1			T2	5		T5	8		T11	1
valid_sources[0x13]	3204	1			T2	2		T5	5		T6	1
valid_sources[0x14]	6669	1			T2	7		T5	13		T6	2
valid_sources[0x15]	3694	1			T2	5		T5	9		T6	4
valid_sources[0x16]	3739	1			T2	2		T5	16		T6	3
valid_sources[0x17]	3836	1			T2	6		T5	11		T11	5
valid_sources[0x18]	3281	1			T2	2		T5	12		T6	1
valid_sources[0x19]	3264	1			T2	6		T5	16		T13	1
valid_sources[0x1a]	3808	1			T2	2		T5	10		T6	2
valid_sources[0x1b]	3289	1			T2	2		T5	6		T13	3
valid_sources[0x1c]	4893	1			T2	1		T5	12		T14	5
valid_sources[0x1d]	3293	1			T2	7		T5	15		T6	1
valid_sources[0x1e]	3802	1			T2	2		T5	6		T54	9
valid_sources[0x1f]	6351	1			T2	5		T4	3200		T5	10
valid_sources[0x20]	4614	1			T2	1		T5	14		T13	2
valid_sources[0x21]	3646	1			T2	3		T5	11		T6	2
valid_sources[0x22]	4514	1			T2	3		T5	6		T7	24
valid_sources[0x23]	3522	1			T2	2		T5	15		T13	1
valid_sources[0x24]	3523	1			T2	2		T5	10		T7	9
valid_sources[0x25]	3163	1			T2	1		T5	8		T6	1
valid_sources[0x26]	3741	1			T2	1		T5	9		T6	1
valid_sources[0x27]	3708	1			T2	4		T5	13		T14	19
valid_sources[0x28]	4058	1			T2	3		T5	21		T13	2
valid_sources[0x29]	3334	1			T2	2		T5	19		T14	48
valid_sources[0x2a]	2925	1			T2	1		T5	14		T6	1
valid_sources[0x2b]	3041	1			T2	2		T5	13		T13	1
valid_sources[0x2c]	4020	1			T2	4		T5	7		T6	1
valid_sources[0x2d]	4058	1			T2	7		T5	6		T6	2
valid_sources[0x2e]	7633	1			T2	2		T5	16		T6	1
valid_sources[0x2f]	4176	1			T2	2		T5	10		T6	1
valid_sources[0x30]	5096	1			T2	3		T5	15		T6	1
valid_sources[0x31]	3768	1			T2	3		T5	6		T6	1
valid_sources[0x32]	3937	1			T1	1		T2	2		T5	12
valid_sources[0x33]	4380	1			T2	1		T5	11		T7	6
valid_sources[0x34]	3689	1			T2	2		T5	21		T13	1
valid_sources[0x35]	3207	1			T2	5		T5	11		T7	17
valid_sources[0x36]	4292	1			T2	3		T5	8		T6	2
valid_sources[0x37]	3793	1			T2	4		T5	15		T6	1
valid_sources[0x38]	3934	1			T2	4		T5	11		T13	1
valid_sources[0x39]	3920	1			T2	2		T5	15		T7	4
valid_sources[0x3a]	3360	1			T2	3		T5	24		T6	1
valid_sources[0x3b]	4100	1			T2	1		T5	11		T7	1
valid_sources[0x3c]	5403	1			T2	4		T5	15		T7	31
valid_sources[0x3d]	3961	1			T2	1		T5	11		T6	1
valid_sources[0x3e]	8524	1			T2	3		T5	14		T7	9
valid_sources[0x3f]	3773	1			T2	1		T5	16		T6	2
valid_sources[0x40]	3229	1			T2	5		T5	16		T6	1
valid_sources[0x41]	3196	1			T2	6		T5	11		T6	1
valid_sources[0x42]	3585	1			T2	4		T5	20		T6	2
valid_sources[0x43]	3936	1			T2	1		T5	12		T13	1
valid_sources[0x44]	3786	1			T2	2		T5	9		T6	1
valid_sources[0x45]	3232	1			T2	4		T5	13		T7	1
valid_sources[0x46]	2885	1			T2	3		T5	15		T6	1
valid_sources[0x47]	3367	1			T2	3		T5	22		T6	1
valid_sources[0x48]	3538	1			T5	9		T7	1		T13	4
valid_sources[0x49]	3395	1			T2	2		T5	20		T54	5
valid_sources[0x4a]	4546	1			T2	1		T5	7		T13	2
valid_sources[0x4b]	4191	1			T2	3		T5	12		T7	35
valid_sources[0x4c]	3291	1			T2	2		T5	6		T6	2
valid_sources[0x4d]	3056	1			T5	14		T11	1		T14	11
valid_sources[0x4e]	3429	1			T2	2		T5	15		T6	2
valid_sources[0x4f]	3332	1			T5	19		T15	2		T54	4
valid_sources[0x50]	5216	1			T2	1		T5	12		T7	7
valid_sources[0x51]	4482	1			T2	5		T5	12		T7	4
valid_sources[0x52]	4056	1			T2	1		T5	9		T6	1
valid_sources[0x53]	4740	1			T2	3		T5	9		T13	1
valid_sources[0x54]	4487	1			T2	4		T5	16		T6	1
valid_sources[0x55]	4637	1			T2	1		T5	16		T6	1
valid_sources[0x56]	3955	1			T2	4		T5	5		T7	13
valid_sources[0x57]	3695	1			T2	1		T5	17		T7	24
valid_sources[0x58]	3291	1			T5	10		T7	19		T13	3
valid_sources[0x59]	4564	1			T1	1		T2	1		T5	15
valid_sources[0x5a]	3993	1			T2	3		T5	17		T54	6
valid_sources[0x5b]	5068	1			T2	2		T5	18		T11	1
valid_sources[0x5c]	3455	1			T2	4		T5	9		T11	1
valid_sources[0x5d]	5089	1			T2	5		T5	7		T6	2
valid_sources[0x5e]	3856	1			T2	3		T5	18		T6	1
valid_sources[0x5f]	4233	1			T2	5		T5	8		T54	9
valid_sources[0x60]	3226	1			T2	2		T5	20		T6	1
valid_sources[0x61]	3968	1			T2	3		T5	10		T6	2
valid_sources[0x62]	4990	1			T2	1		T5	14		T6	1
valid_sources[0x63]	3536	1			T2	1		T5	12		T6	2
valid_sources[0x64]	4430	1			T2	1		T5	15		T13	1
valid_sources[0x65]	3882	1			T2	3		T5	7		T7	9
valid_sources[0x66]	3509	1			T2	2		T5	13		T6	1
valid_sources[0x67]	3674	1			T2	4		T5	13		T6	1
valid_sources[0x68]	3624	1			T2	4		T5	14		T13	1
valid_sources[0x69]	3619	1			T2	3		T3	20		T5	7
valid_sources[0x6a]	3632	1			T2	4		T5	10		T13	1
valid_sources[0x6b]	4328	1			T2	1		T5	11		T6	1
valid_sources[0x6c]	2986	1			T2	4		T5	16		T6	2
valid_sources[0x6d]	3692	1			T2	5		T5	13		T6	1
valid_sources[0x6e]	4014	1			T2	6		T5	9		T6	1
valid_sources[0x6f]	3643	1			T2	2		T5	14		T6	2
valid_sources[0x70]	4446	1			T2	2		T5	19		T6	1
valid_sources[0x71]	2706	1			T2	5		T5	8		T13	2
valid_sources[0x72]	3403	1			T2	2		T5	16		T13	3
valid_sources[0x73]	4071	1			T2	2		T5	15		T6	1
valid_sources[0x74]	3823	1			T2	5		T5	7		T6	1
valid_sources[0x75]	3693	1			T2	1		T5	8		T11	4
valid_sources[0x76]	4474	1			T2	2		T5	8		T6	1
valid_sources[0x77]	3362	1			T2	3		T5	7		T7	8
valid_sources[0x78]	4036	1			T2	2		T5	16		T7	25
valid_sources[0x79]	3281	1			T2	3		T5	14		T6	3
valid_sources[0x7a]	3793	1			T2	4		T5	7		T6	3
valid_sources[0x7b]	6072	1			T5	7		T6	1		T13	1
valid_sources[0x7c]	4359	1			T2	3		T5	2		T6	1
valid_sources[0x7d]	3437	1			T1	1		T2	4		T5	11
valid_sources[0x7e]	3478	1			T2	6		T5	9		T7	5
valid_sources[0x7f]	3367	1			T1	1		T2	3		T5	14
valid_sources[0x80]	6927	1			T2	2		T5	12		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

250109

1

T1

6

T2

211

T4

666

values[0x0]

all_enables

biggest_size

81573

1

T1

1

T2

72

T4

270

values[0x1]

all_enables

biggest_size

42843

1

T1

2

T2

26

T4

141