Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T15,T27
0	1	Covered	T27,T32,T34
1	0	Covered	T32,T34,T69

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T6,T15,T27
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57126345	9468	0	0
CascadeEffAonToRstPorAboveRise_A	57126345	9468	0	0
CascadeEffAonToRstPorIoAboveFall_A	54839640	9468	0	0
CascadeEffAonToRstPorIoAboveRise_A	54839640	9468	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27420661	9468	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27420661	9468	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13710007	9468	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13710007	9468	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27420767	9468	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27420767	9468	0	0
CascadeLcToLcAboveFall_A	57126345	22882	0	0
CascadeLcToLcAboveRise_A	57126345	22882	0	0
CascadeLcToLcAonAboveFall_A	1730867	22882	0	0
CascadeLcToLcAonAboveRise_A	1730867	22882	0	0
CascadeLcToLcShadowedAboveFall_A	57126345	22882	0	0
CascadeLcToLcShadowedAboveRise_A	57126345	22882	0	0
CascadePorToAonAboveFall_A	1730867	7575	0	0
CascadeSysToSysAboveFall_A	57126345	22882	0	0
CascadeSysToSysAboveRise_A	57126345	22882	0	0
ScanRstToAonRise_A	1730867	221	0	0
StablePorToAonRise_A	1730867	9468	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12144507	22882	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12144507	22882	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12144507	22882	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12144507	22882	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13710007	22882	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13710007	22882	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12144507	22882	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12144507	22882	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12144507	22882	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12144507	22882	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57126345	9468	0	0
T1	7826	1	0	0
T2	12761	1	0	0
T3	164335	541	0	0
T4	122046	27	0	0
T5	122206	27	0	0
T6	10851	2	0	0
T7	33562	1	0	0
T8	24257	8	0	0
T9	24372	8	0	0
T10	235642	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57126345	9468	0	0
T1	7826	1	0	0
T2	12761	1	0	0
T3	164335	541	0	0
T4	122046	27	0	0
T5	122206	27	0	0
T6	10851	2	0	0
T7	33562	1	0	0
T8	24257	8	0	0
T9	24372	8	0	0
T10	235642	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54839640	9468	0	0
T1	7512	1	0	0
T2	12249	1	0	0
T3	157754	541	0	0
T4	117177	27	0	0
T5	117313	27	0	0
T6	10418	2	0	0
T7	32219	1	0	0
T8	23282	8	0	0
T9	23401	8	0	0
T10	226198	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54839640	9468	0	0
T1	7512	1	0	0
T2	12249	1	0	0
T3	157754	541	0	0
T4	117177	27	0	0
T5	117313	27	0	0
T6	10418	2	0	0
T7	32219	1	0	0
T8	23282	8	0	0
T9	23401	8	0	0
T10	226198	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420661	9468	0	0
T1	3756	1	0	0
T2	6126	1	0	0
T3	788801	541	0	0
T4	58586	27	0	0
T5	58662	27	0	0
T6	5209	2	0	0
T7	16110	1	0	0
T8	11647	8	0	0
T9	11697	8	0	0
T10	113115	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420661	9468	0	0
T1	3756	1	0	0
T2	6126	1	0	0
T3	788801	541	0	0
T4	58586	27	0	0
T5	58662	27	0	0
T6	5209	2	0	0
T7	16110	1	0	0
T8	11647	8	0	0
T9	11697	8	0	0
T10	113115	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	9468	0	0
T1	1877	1	0	0
T2	3061	1	0	0
T3	394324	541	0	0
T4	29291	27	0	0
T5	29325	27	0	0
T6	2603	2	0	0
T7	8054	1	0	0
T8	5819	8	0	0
T9	5851	8	0	0
T10	56549	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	9468	0	0
T1	1877	1	0	0
T2	3061	1	0	0
T3	394324	541	0	0
T4	29291	27	0	0
T5	29325	27	0	0
T6	2603	2	0	0
T7	8054	1	0	0
T8	5819	8	0	0
T9	5851	8	0	0
T10	56549	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420767	9468	0	0
T1	3755	1	0	0
T2	6126	1	0	0
T3	788810	541	0	0
T4	58576	27	0	0
T5	58653	27	0	0
T6	5207	2	0	0
T7	16110	1	0	0
T8	11655	8	0	0
T9	11698	8	0	0
T10	113103	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420767	9468	0	0
T1	3755	1	0	0
T2	6126	1	0	0
T3	788810	541	0	0
T4	58576	27	0	0
T5	58653	27	0	0
T6	5207	2	0	0
T7	16110	1	0	0
T8	11655	8	0	0
T9	11698	8	0	0
T10	113103	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57126345	22882	0	0
T1	7826	2	0	0
T2	12761	1	0	0
T3	164335	541	0	0
T4	122046	102	0	0
T5	122206	102	0	0
T6	10851	6	0	0
T7	33562	1	0	0
T8	24257	8	0	0
T9	24372	8	0	0
T10	235642	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57126345	22882	0	0
T1	7826	2	0	0
T2	12761	1	0	0
T3	164335	541	0	0
T4	122046	102	0	0
T5	122206	102	0	0
T6	10851	6	0	0
T7	33562	1	0	0
T8	24257	8	0	0
T9	24372	8	0	0
T10	235642	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730867	22882	0	0
T1	233	2	0	0
T2	381	1	0	0
T3	49546	541	0	0
T4	3676	102	0	0
T5	3681	102	0	0
T6	325	6	0	0
T7	1005	1	0	0
T8	730	8	0	0
T9	732	8	0	0
T10	7083	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730867	22882	0	0
T1	233	2	0	0
T2	381	1	0	0
T3	49546	541	0	0
T4	3676	102	0	0
T5	3681	102	0	0
T6	325	6	0	0
T7	1005	1	0	0
T8	730	8	0	0
T9	732	8	0	0
T10	7083	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57126345	22882	0	0
T1	7826	2	0	0
T2	12761	1	0	0
T3	164335	541	0	0
T4	122046	102	0	0
T5	122206	102	0	0
T6	10851	6	0	0
T7	33562	1	0	0
T8	24257	8	0	0
T9	24372	8	0	0
T10	235642	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57126345	22882	0	0
T1	7826	2	0	0
T2	12761	1	0	0
T3	164335	541	0	0
T4	122046	102	0	0
T5	122206	102	0	0
T6	10851	6	0	0
T7	33562	1	0	0
T8	24257	8	0	0
T9	24372	8	0	0
T10	235642	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730867	7575	0	0
T1	233	1	0	0
T2	381	1	0	0
T3	49546	541	0	0
T4	3676	27	0	0
T5	3681	27	0	0
T6	325	1	0	0
T7	1005	1	0	0
T8	730	8	0	0
T9	732	8	0	0
T10	7083	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57126345	22882	0	0
T1	7826	2	0	0
T2	12761	1	0	0
T3	164335	541	0	0
T4	122046	102	0	0
T5	122206	102	0	0
T6	10851	6	0	0
T7	33562	1	0	0
T8	24257	8	0	0
T9	24372	8	0	0
T10	235642	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57126345	22882	0	0
T1	7826	2	0	0
T2	12761	1	0	0
T3	164335	541	0	0
T4	122046	102	0	0
T5	122206	102	0	0
T6	10851	6	0	0
T7	33562	1	0	0
T8	24257	8	0	0
T9	24372	8	0	0
T10	235642	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730867	221	0	0
T19	601	0	0	0
T20	617	0	0	0
T34	2467	1	0	0
T63	50184	0	0	0
T65	218	0	0	0
T69	5659	0	0	0
T70	22638	8	0	0
T71	574	0	0	0
T72	0	4	0	0
T73	0	6	0	0
T77	325	0	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	1	0	0
T88	0	2	0	0
T89	0	2	0	0
T119	0	2	0	0
T120	730	0	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730867	9468	0	0
T1	233	1	0	0
T2	381	1	0	0
T3	49546	541	0	0
T4	3676	27	0	0
T5	3681	27	0	0
T6	325	2	0	0
T7	1005	1	0	0
T8	730	8	0	0
T9	732	8	0	0
T10	7083	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144507	22882	0	0
T1	1731	2	0	0
T2	3019	1	0	0
T3	357424	541	0	0
T4	26141	102	0	0
T5	26253	102	0	0
T6	2266	6	0	0
T7	7987	1	0	0
T8	5086	8	0	0
T9	5496	8	0	0
T10	53480	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144507	22882	0	0
T1	1731	2	0	0
T2	3019	1	0	0
T3	357424	541	0	0
T4	26141	102	0	0
T5	26253	102	0	0
T6	2266	6	0	0
T7	7987	1	0	0
T8	5086	8	0	0
T9	5496	8	0	0
T10	53480	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144507	22882	0	0
T1	1731	2	0	0
T2	3019	1	0	0
T3	357424	541	0	0
T4	26141	102	0	0
T5	26253	102	0	0
T6	2266	6	0	0
T7	7987	1	0	0
T8	5086	8	0	0
T9	5496	8	0	0
T10	53480	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144507	22882	0	0
T1	1731	2	0	0
T2	3019	1	0	0
T3	357424	541	0	0
T4	26141	102	0	0
T5	26253	102	0	0
T6	2266	6	0	0
T7	7987	1	0	0
T8	5086	8	0	0
T9	5496	8	0	0
T10	53480	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	22882	0	0
T1	1877	2	0	0
T2	3061	1	0	0
T3	394324	541	0	0
T4	29291	102	0	0
T5	29325	102	0	0
T6	2603	6	0	0
T7	8054	1	0	0
T8	5819	8	0	0
T9	5851	8	0	0
T10	56549	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	22882	0	0
T1	1877	2	0	0
T2	3061	1	0	0
T3	394324	541	0	0
T4	29291	102	0	0
T5	29325	102	0	0
T6	2603	6	0	0
T7	8054	1	0	0
T8	5819	8	0	0
T9	5851	8	0	0
T10	56549	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144507	22882	0	0
T1	1731	2	0	0
T2	3019	1	0	0
T3	357424	541	0	0
T4	26141	102	0	0
T5	26253	102	0	0
T6	2266	6	0	0
T7	7987	1	0	0
T8	5086	8	0	0
T9	5496	8	0	0
T10	53480	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144507	22882	0	0
T1	1731	2	0	0
T2	3019	1	0	0
T3	357424	541	0	0
T4	26141	102	0	0
T5	26253	102	0	0
T6	2266	6	0	0
T7	7987	1	0	0
T8	5086	8	0	0
T9	5496	8	0	0
T10	53480	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144507	22882	0	0
T1	1731	2	0	0
T2	3019	1	0	0
T3	357424	541	0	0
T4	26141	102	0	0
T5	26253	102	0	0
T6	2266	6	0	0
T7	7987	1	0	0
T8	5086	8	0	0
T9	5496	8	0	0
T10	53480	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144507	22882	0	0
T1	1731	2	0	0
T2	3019	1	0	0
T3	357424	541	0	0
T4	26141	102	0	0
T5	26253	102	0	0
T6	2266	6	0	0
T7	7987	1	0	0
T8	5086	8	0	0
T9	5496	8	0	0
T10	53480	102	0	0