Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T12
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T12
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T54
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T12
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T12
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T54
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T54
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13710007	14337	0	0
gen_assertions[0].RstEnOn_A	13710007	1118	0	0
gen_assertions[0].RstNOff_A	13710007	14337	0	0
gen_assertions[0].RstNOn_A	13710007	1118	0	0
gen_assertions[1].RstEnOff_A	54839640	13030	0	0
gen_assertions[1].RstEnOn_A	54839640	1051	0	0
gen_assertions[1].RstNOff_A	54839640	13030	0	0
gen_assertions[1].RstNOn_A	54839640	1051	0	0
gen_assertions[2].RstEnOff_A	27420661	13134	0	0
gen_assertions[2].RstEnOn_A	27420661	1100	0	0
gen_assertions[2].RstNOff_A	27420661	13134	0	0
gen_assertions[2].RstNOn_A	27420661	1100	0	0
gen_assertions[3].RstEnOff_A	27420767	13138	0	0
gen_assertions[3].RstEnOn_A	27420767	1095	0	0
gen_assertions[3].RstNOff_A	27420767	13138	0	0
gen_assertions[3].RstNOn_A	27420767	1095	0	0
gen_assertions[4].RstEnOff_A	1730867	22732	0	0
gen_assertions[4].RstEnOn_A	1730867	1169	0	0
gen_assertions[4].RstNOff_A	1730867	22732	0	0
gen_assertions[4].RstNOn_A	1730867	1169	0	0
gen_assertions[5].RstEnOff_A	13710007	14573	0	0
gen_assertions[5].RstEnOn_A	13710007	1194	0	0
gen_assertions[5].RstNOff_A	13710007	14573	0	0
gen_assertions[5].RstNOn_A	13710007	1194	0	0
gen_assertions[6].RstEnOff_A	13710007	14663	0	0
gen_assertions[6].RstEnOn_A	13710007	1292	0	0
gen_assertions[6].RstNOff_A	13710007	14663	0	0
gen_assertions[6].RstNOn_A	13710007	1292	0	0
gen_assertions[7].RstEnOff_A	13710007	14690	0	0
gen_assertions[7].RstEnOn_A	13710007	1311	0	0
gen_assertions[7].RstNOff_A	13710007	14690	0	0
gen_assertions[7].RstNOn_A	13710007	1311	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	14337	0	0
T1	1877	1	0	0
T2	3061	2	0	0
T3	394324	0	0	0
T4	29291	75	0	0
T5	29325	75	0	0
T6	2603	4	0	0
T7	8054	5	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	75	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	13	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	1118	0	0
T2	3061	2	0	0
T3	394324	0	0	0
T4	29291	0	0	0
T5	29325	0	0	0
T6	2603	0	0	0
T7	8054	5	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	0	0	0
T11	2457	1	0	0
T12	0	1	0	0
T13	0	5	0	0
T16	0	1	0	0
T54	0	9	0	0
T74	0	9	0	0
T75	0	1	0	0
T76	0	2	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	14337	0	0
T1	1877	1	0	0
T2	3061	2	0	0
T3	394324	0	0	0
T4	29291	75	0	0
T5	29325	75	0	0
T6	2603	4	0	0
T7	8054	5	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	75	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	13	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	1118	0	0
T2	3061	2	0	0
T3	394324	0	0	0
T4	29291	0	0	0
T5	29325	0	0	0
T6	2603	0	0	0
T7	8054	5	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	0	0	0
T11	2457	1	0	0
T12	0	1	0	0
T13	0	5	0	0
T16	0	1	0	0
T54	0	9	0	0
T74	0	9	0	0
T75	0	1	0	0
T76	0	2	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54839640	13030	0	0
T1	7512	1	0	0
T2	12249	4	0	0
T3	157754	0	0	0
T4	117177	71	0	0
T5	117313	63	0	0
T6	10418	4	0	0
T7	32219	6	0	0
T8	23282	0	0	0
T9	23401	0	0	0
T10	226198	69	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	10	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54839640	1051	0	0
T2	12249	4	0	0
T3	157754	0	0	0
T4	117177	0	0	0
T5	117313	0	0	0
T6	10418	0	0	0
T7	32219	6	0	0
T8	23282	0	0	0
T9	23401	0	0	0
T10	226198	0	0	0
T11	9832	0	0	0
T12	0	1	0	0
T13	0	3	0	0
T28	0	7	0	0
T30	0	5	0	0
T54	0	9	0	0
T74	0	7	0	0
T75	0	2	0	0
T77	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54839640	13030	0	0
T1	7512	1	0	0
T2	12249	4	0	0
T3	157754	0	0	0
T4	117177	71	0	0
T5	117313	63	0	0
T6	10418	4	0	0
T7	32219	6	0	0
T8	23282	0	0	0
T9	23401	0	0	0
T10	226198	69	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	10	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54839640	1051	0	0
T2	12249	4	0	0
T3	157754	0	0	0
T4	117177	0	0	0
T5	117313	0	0	0
T6	10418	0	0	0
T7	32219	6	0	0
T8	23282	0	0	0
T9	23401	0	0	0
T10	226198	0	0	0
T11	9832	0	0	0
T12	0	1	0	0
T13	0	3	0	0
T28	0	7	0	0
T30	0	5	0	0
T54	0	9	0	0
T74	0	7	0	0
T75	0	2	0	0
T77	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420661	13134	0	0
T1	3756	1	0	0
T2	6126	5	0	0
T3	788801	0	0	0
T4	58586	71	0	0
T5	58662	63	0	0
T6	5209	4	0	0
T7	16110	7	0	0
T8	11647	0	0	0
T9	11697	0	0	0
T10	113115	69	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	10	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420661	1100	0	0
T2	6126	5	0	0
T3	788801	0	0	0
T4	58586	0	0	0
T5	58662	0	0	0
T6	5209	0	0	0
T7	16110	7	0	0
T8	11647	0	0	0
T9	11697	0	0	0
T10	113115	0	0	0
T11	4916	0	0	0
T12	0	1	0	0
T28	0	10	0	0
T30	0	7	0	0
T54	0	10	0	0
T70	0	19	0	0
T74	0	10	0	0
T75	0	3	0	0
T77	0	2	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420661	13134	0	0
T1	3756	1	0	0
T2	6126	5	0	0
T3	788801	0	0	0
T4	58586	71	0	0
T5	58662	63	0	0
T6	5209	4	0	0
T7	16110	7	0	0
T8	11647	0	0	0
T9	11697	0	0	0
T10	113115	69	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	10	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420661	1100	0	0
T2	6126	5	0	0
T3	788801	0	0	0
T4	58586	0	0	0
T5	58662	0	0	0
T6	5209	0	0	0
T7	16110	7	0	0
T8	11647	0	0	0
T9	11697	0	0	0
T10	113115	0	0	0
T11	4916	0	0	0
T12	0	1	0	0
T28	0	10	0	0
T30	0	7	0	0
T54	0	10	0	0
T70	0	19	0	0
T74	0	10	0	0
T75	0	3	0	0
T77	0	2	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420767	13138	0	0
T1	3755	1	0	0
T2	6126	4	0	0
T3	788810	0	0	0
T4	58576	71	0	0
T5	58653	63	0	0
T6	5207	4	0	0
T7	16110	8	0	0
T8	11655	0	0	0
T9	11698	0	0	0
T10	113103	69	0	0
T11	0	5	0	0
T13	0	10	0	0
T14	0	68	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420767	1095	0	0
T2	6126	4	0	0
T3	788810	0	0	0
T4	58576	0	0	0
T5	58653	0	0	0
T6	5207	0	0	0
T7	16110	8	0	0
T8	11655	0	0	0
T9	11698	0	0	0
T10	113103	0	0	0
T11	4915	0	0	0
T28	0	10	0	0
T30	0	6	0	0
T54	0	10	0	0
T70	0	17	0	0
T71	0	1	0	0
T74	0	10	0	0
T75	0	4	0	0
T77	0	4	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420767	13138	0	0
T1	3755	1	0	0
T2	6126	4	0	0
T3	788810	0	0	0
T4	58576	71	0	0
T5	58653	63	0	0
T6	5207	4	0	0
T7	16110	8	0	0
T8	11655	0	0	0
T9	11698	0	0	0
T10	113103	69	0	0
T11	0	5	0	0
T13	0	10	0	0
T14	0	68	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27420767	1095	0	0
T2	6126	4	0	0
T3	788810	0	0	0
T4	58576	0	0	0
T5	58653	0	0	0
T6	5207	0	0	0
T7	16110	8	0	0
T8	11655	0	0	0
T9	11698	0	0	0
T10	113103	0	0	0
T11	4915	0	0	0
T28	0	10	0	0
T30	0	6	0	0
T54	0	10	0	0
T70	0	17	0	0
T71	0	1	0	0
T74	0	10	0	0
T75	0	4	0	0
T77	0	4	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730867	22732	0	0
T1	233	2	0	0
T2	381	8	0	0
T3	49546	541	0	0
T4	3676	76	0	0
T5	3681	75	0	0
T6	325	5	0	0
T7	1005	11	0	0
T8	730	2	0	0
T9	732	3	0	0
T10	7083	96	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730867	1169	0	0
T2	381	7	0	0
T3	49546	0	0	0
T4	3676	0	0	0
T5	3681	0	0	0
T6	325	0	0	0
T7	1005	10	0	0
T8	730	0	0	0
T9	732	0	0	0
T10	7083	0	0	0
T11	306	0	0	0
T12	0	1	0	0
T28	0	11	0	0
T30	0	8	0	0
T54	0	12	0	0
T70	0	17	0	0
T74	0	10	0	0
T75	0	5	0	0
T77	0	4	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730867	22732	0	0
T1	233	2	0	0
T2	381	8	0	0
T3	49546	541	0	0
T4	3676	76	0	0
T5	3681	75	0	0
T6	325	5	0	0
T7	1005	11	0	0
T8	730	2	0	0
T9	732	3	0	0
T10	7083	96	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730867	1169	0	0
T2	381	7	0	0
T3	49546	0	0	0
T4	3676	0	0	0
T5	3681	0	0	0
T6	325	0	0	0
T7	1005	10	0	0
T8	730	0	0	0
T9	732	0	0	0
T10	7083	0	0	0
T11	306	0	0	0
T12	0	1	0	0
T28	0	11	0	0
T30	0	8	0	0
T54	0	12	0	0
T70	0	17	0	0
T74	0	10	0	0
T75	0	5	0	0
T77	0	4	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	14573	0	0
T1	1877	1	0	0
T2	3061	8	0	0
T3	394324	0	0	0
T4	29291	75	0	0
T5	29325	75	0	0
T6	2603	4	0	0
T7	8054	9	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	75	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	13	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	1194	0	0
T2	3061	8	0	0
T3	394324	0	0	0
T4	29291	0	0	0
T5	29325	0	0	0
T6	2603	0	0	0
T7	8054	9	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	0	0	0
T11	2457	0	0	0
T12	0	1	0	0
T28	0	12	0	0
T30	0	11	0	0
T54	0	10	0	0
T70	0	22	0	0
T74	0	12	0	0
T75	0	7	0	0
T77	0	5	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	14573	0	0
T1	1877	1	0	0
T2	3061	8	0	0
T3	394324	0	0	0
T4	29291	75	0	0
T5	29325	75	0	0
T6	2603	4	0	0
T7	8054	9	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	75	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	13	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	1194	0	0
T2	3061	8	0	0
T3	394324	0	0	0
T4	29291	0	0	0
T5	29325	0	0	0
T6	2603	0	0	0
T7	8054	9	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	0	0	0
T11	2457	0	0	0
T12	0	1	0	0
T28	0	12	0	0
T30	0	11	0	0
T54	0	10	0	0
T70	0	22	0	0
T74	0	12	0	0
T75	0	7	0	0
T77	0	5	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	14663	0	0
T1	1877	1	0	0
T2	3061	9	0	0
T3	394324	0	0	0
T4	29291	75	0	0
T5	29325	75	0	0
T6	2603	4	0	0
T7	8054	11	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	75	0	0
T11	0	5	0	0
T13	0	13	0	0
T14	0	75	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	1292	0	0
T2	3061	9	0	0
T3	394324	0	0	0
T4	29291	0	0	0
T5	29325	0	0	0
T6	2603	0	0	0
T7	8054	11	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	0	0	0
T11	2457	0	0	0
T28	0	15	0	0
T30	0	11	0	0
T54	0	14	0	0
T70	0	22	0	0
T71	0	1	0	0
T74	0	14	0	0
T75	0	7	0	0
T77	0	7	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	14663	0	0
T1	1877	1	0	0
T2	3061	9	0	0
T3	394324	0	0	0
T4	29291	75	0	0
T5	29325	75	0	0
T6	2603	4	0	0
T7	8054	11	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	75	0	0
T11	0	5	0	0
T13	0	13	0	0
T14	0	75	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	1292	0	0
T2	3061	9	0	0
T3	394324	0	0	0
T4	29291	0	0	0
T5	29325	0	0	0
T6	2603	0	0	0
T7	8054	11	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	0	0	0
T11	2457	0	0	0
T28	0	15	0	0
T30	0	11	0	0
T54	0	14	0	0
T70	0	22	0	0
T71	0	1	0	0
T74	0	14	0	0
T75	0	7	0	0
T77	0	7	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	14690	0	0
T1	1877	1	0	0
T2	3061	11	0	0
T3	394324	0	0	0
T4	29291	75	0	0
T5	29325	75	0	0
T6	2603	4	0	0
T7	8054	13	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	75	0	0
T11	0	5	0	0
T13	0	13	0	0
T14	0	75	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	1311	0	0
T2	3061	11	0	0
T3	394324	0	0	0
T4	29291	0	0	0
T5	29325	0	0	0
T6	2603	0	0	0
T7	8054	13	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	0	0	0
T11	2457	0	0	0
T28	0	13	0	0
T30	0	13	0	0
T54	0	13	0	0
T70	0	18	0	0
T72	0	20	0	0
T74	0	14	0	0
T75	0	9	0	0
T77	0	7	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	14690	0	0
T1	1877	1	0	0
T2	3061	11	0	0
T3	394324	0	0	0
T4	29291	75	0	0
T5	29325	75	0	0
T6	2603	4	0	0
T7	8054	13	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	75	0	0
T11	0	5	0	0
T13	0	13	0	0
T14	0	75	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13710007	1311	0	0
T2	3061	11	0	0
T3	394324	0	0	0
T4	29291	0	0	0
T5	29325	0	0	0
T6	2603	0	0	0
T7	8054	13	0	0
T8	5819	0	0	0
T9	5851	0	0	0
T10	56549	0	0	0
T11	2457	0	0	0
T28	0	13	0	0
T30	0	13	0	0
T54	0	13	0	0
T70	0	18	0	0
T72	0	20	0	0
T74	0	14	0	0
T75	0	9	0	0
T77	0	7	0	0