Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13002469	8123	0	0
alert_regwen_rd_A	13002469	5430	0	0
cpu_regwen_rd_A	13002469	5795	0	0
sw_rst_ctrl_n_0_rd_A	13002469	10181	0	0
sw_rst_ctrl_n_1_rd_A	13002469	10605	0	0
sw_rst_ctrl_n_2_rd_A	13002469	10189	0	0
sw_rst_ctrl_n_3_rd_A	13002469	10582	0	0
sw_rst_ctrl_n_4_rd_A	13002469	10339	0	0
sw_rst_ctrl_n_5_rd_A	13002469	10555	0	0
sw_rst_ctrl_n_6_rd_A	13002469	10433	0	0
sw_rst_ctrl_n_7_rd_A	13002469	10460	0	0
sw_rst_regwen_0_rd_A	13002469	6210	0	0
sw_rst_regwen_1_rd_A	13002469	6143	0	0
sw_rst_regwen_2_rd_A	13002469	6242	0	0
sw_rst_regwen_3_rd_A	13002469	6158	0	0
sw_rst_regwen_4_rd_A	13002469	6016	0	0
sw_rst_regwen_5_rd_A	13002469	6292	0	0
sw_rst_regwen_6_rd_A	13002469	6026	0	0
sw_rst_regwen_7_rd_A	13002469	6173	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	8123	0	0
T56	4295	71	0	0
T59	3373	63	0	0
T60	2388	47	0	0
T61	4252	455	0	0
T62	8426	284	0	0
T66	20794	2	0	0
T78	4311	93	0	0
T79	3168	14	0	0
T80	12979	546	0	0
T81	4752	517	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	5430	0	0
T18	4138	0	0	0
T19	4709	0	0	0
T32	41856	46	0	0
T33	48768	0	0	0
T34	14970	0	0	0
T63	349553	0	0	0
T65	1666	0	0	0
T69	39425	61	0	0
T70	138050	0	0	0
T73	0	389	0	0
T77	2545	0	0	0
T83	0	343	0	0
T86	0	13	0	0
T89	0	209	0	0
T109	0	197	0	0
T110	0	47	0	0
T111	0	465	0	0
T112	0	332	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	5795	0	0
T18	4138	0	0	0
T19	4709	0	0	0
T32	41856	42	0	0
T33	48768	0	0	0
T34	14970	0	0	0
T63	349553	0	0	0
T65	1666	0	0	0
T69	39425	52	0	0
T70	138050	0	0	0
T73	0	420	0	0
T77	2545	0	0	0
T83	0	390	0	0
T86	0	6	0	0
T89	0	193	0	0
T109	0	177	0	0
T110	0	61	0	0
T111	0	450	0	0
T112	0	345	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	10181	0	0
T1	1731	4	0	0
T2	3019	0	0	0
T3	357424	0	0	0
T4	26141	0	0	0
T5	26253	0	0	0
T6	2266	0	0	0
T7	7987	0	0	0
T8	5086	0	0	0
T9	5496	0	0	0
T10	53480	0	0	0
T16	0	9	0	0
T28	0	194	0	0
T32	0	50	0	0
T69	0	41	0	0
T73	0	583	0	0
T76	0	38	0	0
T83	0	667	0	0
T113	0	54	0	0
T114	0	177	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	10605	0	0
T1	1731	5	0	0
T2	3019	0	0	0
T3	357424	0	0	0
T4	26141	0	0	0
T5	26253	0	0	0
T6	2266	0	0	0
T7	7987	0	0	0
T8	5086	0	0	0
T9	5496	0	0	0
T10	53480	0	0	0
T28	0	233	0	0
T32	0	42	0	0
T69	0	56	0	0
T73	0	536	0	0
T76	0	39	0	0
T83	0	704	0	0
T86	0	33	0	0
T113	0	65	0	0
T114	0	148	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	10189	0	0
T1	1731	1	0	0
T2	3019	0	0	0
T3	357424	0	0	0
T4	26141	0	0	0
T5	26253	0	0	0
T6	2266	0	0	0
T7	7987	0	0	0
T8	5086	0	0	0
T9	5496	0	0	0
T10	53480	0	0	0
T16	0	1	0	0
T28	0	227	0	0
T32	0	33	0	0
T69	0	45	0	0
T73	0	532	0	0
T76	0	29	0	0
T83	0	633	0	0
T113	0	86	0	0
T114	0	138	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	10582	0	0
T1	1731	2	0	0
T2	3019	0	0	0
T3	357424	0	0	0
T4	26141	0	0	0
T5	26253	0	0	0
T6	2266	0	0	0
T7	7987	0	0	0
T8	5086	0	0	0
T9	5496	0	0	0
T10	53480	0	0	0
T28	0	167	0	0
T32	0	35	0	0
T69	0	73	0	0
T73	0	535	0	0
T76	0	28	0	0
T83	0	661	0	0
T86	0	71	0	0
T113	0	49	0	0
T114	0	168	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	10339	0	0
T1	1731	5	0	0
T2	3019	0	0	0
T3	357424	0	0	0
T4	26141	0	0	0
T5	26253	0	0	0
T6	2266	0	0	0
T7	7987	0	0	0
T8	5086	0	0	0
T9	5496	0	0	0
T10	53480	0	0	0
T16	0	2	0	0
T28	0	216	0	0
T32	0	41	0	0
T69	0	58	0	0
T73	0	510	0	0
T76	0	24	0	0
T83	0	703	0	0
T113	0	73	0	0
T114	0	153	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	10555	0	0
T16	1797	2	0	0
T17	3583	0	0	0
T27	2395	0	0	0
T28	0	222	0	0
T32	0	33	0	0
T48	1371	0	0	0
T49	26097	0	0	0
T69	0	50	0	0
T73	0	585	0	0
T74	3604	0	0	0
T75	2649	0	0	0
T76	2992	21	0	0
T83	0	657	0	0
T86	0	76	0	0
T113	0	45	0	0
T114	0	168	0	0
T115	5671	0	0	0
T116	1497	0	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	10433	0	0
T1	1731	8	0	0
T2	3019	0	0	0
T3	357424	0	0	0
T4	26141	0	0	0
T5	26253	0	0	0
T6	2266	0	0	0
T7	7987	0	0	0
T8	5086	0	0	0
T9	5496	0	0	0
T10	53480	0	0	0
T16	0	2	0	0
T28	0	216	0	0
T32	0	51	0	0
T69	0	74	0	0
T73	0	575	0	0
T76	0	20	0	0
T83	0	672	0	0
T113	0	56	0	0
T114	0	130	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	10460	0	0
T1	1731	2	0	0
T2	3019	0	0	0
T3	357424	0	0	0
T4	26141	0	0	0
T5	26253	0	0	0
T6	2266	0	0	0
T7	7987	0	0	0
T8	5086	0	0	0
T9	5496	0	0	0
T10	53480	0	0	0
T16	0	6	0	0
T28	0	216	0	0
T32	0	30	0	0
T69	0	50	0	0
T73	0	533	0	0
T76	0	35	0	0
T83	0	697	0	0
T113	0	57	0	0
T114	0	159	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	6210	0	0
T18	4138	0	0	0
T28	12682	27	0	0
T29	2402	0	0	0
T30	3045	0	0	0
T31	5689	0	0	0
T32	41856	32	0	0
T33	48768	0	0	0
T34	14970	0	0	0
T69	39425	55	0	0
T73	0	426	0	0
T77	2545	0	0	0
T83	0	351	0	0
T86	0	32	0	0
T89	0	223	0	0
T114	0	42	0	0
T117	0	40	0	0
T118	0	7	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	6143	0	0
T18	4138	0	0	0
T28	12682	49	0	0
T29	2402	0	0	0
T30	3045	0	0	0
T31	5689	0	0	0
T32	41856	57	0	0
T33	48768	0	0	0
T34	14970	0	0	0
T69	39425	68	0	0
T73	0	409	0	0
T77	2545	0	0	0
T83	0	386	0	0
T86	0	7	0	0
T89	0	223	0	0
T114	0	41	0	0
T117	0	31	0	0
T118	0	4	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	6242	0	0
T18	4138	0	0	0
T28	12682	49	0	0
T29	2402	0	0	0
T30	3045	0	0	0
T31	5689	0	0	0
T32	41856	64	0	0
T33	48768	0	0	0
T34	14970	0	0	0
T69	39425	52	0	0
T73	0	376	0	0
T77	2545	0	0	0
T83	0	343	0	0
T86	0	3	0	0
T89	0	203	0	0
T114	0	47	0	0
T117	0	36	0	0
T118	0	1	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	6158	0	0
T18	4138	0	0	0
T28	12682	24	0	0
T29	2402	0	0	0
T30	3045	0	0	0
T31	5689	0	0	0
T32	41856	53	0	0
T33	48768	0	0	0
T34	14970	0	0	0
T69	39425	42	0	0
T73	0	412	0	0
T77	2545	0	0	0
T83	0	388	0	0
T86	0	19	0	0
T89	0	163	0	0
T114	0	35	0	0
T117	0	21	0	0
T118	0	5	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	6016	0	0
T18	4138	0	0	0
T28	12682	43	0	0
T29	2402	0	0	0
T30	3045	0	0	0
T31	5689	0	0	0
T32	41856	41	0	0
T33	48768	0	0	0
T34	14970	0	0	0
T69	39425	36	0	0
T73	0	392	0	0
T77	2545	0	0	0
T83	0	322	0	0
T86	0	27	0	0
T89	0	207	0	0
T114	0	31	0	0
T117	0	37	0	0
T118	0	13	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	6292	0	0
T18	4138	0	0	0
T28	12682	30	0	0
T29	2402	0	0	0
T30	3045	0	0	0
T31	5689	0	0	0
T32	41856	76	0	0
T33	48768	0	0	0
T34	14970	0	0	0
T69	39425	56	0	0
T73	0	431	0	0
T77	2545	0	0	0
T83	0	437	0	0
T86	0	5	0	0
T89	0	213	0	0
T114	0	45	0	0
T117	0	28	0	0
T118	0	5	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	6026	0	0
T18	4138	0	0	0
T28	12682	23	0	0
T29	2402	0	0	0
T30	3045	0	0	0
T31	5689	0	0	0
T32	41856	29	0	0
T33	48768	0	0	0
T34	14970	0	0	0
T69	39425	57	0	0
T73	0	416	0	0
T77	2545	0	0	0
T83	0	395	0	0
T86	0	18	0	0
T89	0	206	0	0
T114	0	29	0	0
T117	0	24	0	0
T118	0	5	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13002469	6173	0	0
T18	4138	0	0	0
T28	12682	29	0	0
T29	2402	0	0	0
T30	3045	0	0	0
T31	5689	0	0	0
T32	41856	39	0	0
T33	48768	0	0	0
T34	14970	0	0	0
T69	39425	48	0	0
T73	0	404	0	0
T77	2545	0	0	0
T83	0	355	0	0
T86	0	24	0	0
T89	0	160	0	0
T114	0	45	0	0
T117	0	22	0	0
T118	0	11	0	0