Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	608420	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

365956

1

T1

399

T2

64

T3

302

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	518753	1			T1	523		T2	99		T3	451
values[0x0]	227673	1			T1	244		T2	57		T3	212
values[0x1]	227950	1			T1	233		T2	56		T3	193

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	510867	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

463509

1

T1

487

T2

86

T3

386

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3834	1			T1	1		T2	8		T5	18
valid_sources[0x01]	3382	1			T1	11		T5	8		T7	13
valid_sources[0x02]	3390	1			T1	4		T2	13		T5	11
valid_sources[0x03]	3130	1			T1	3		T5	8		T7	17
valid_sources[0x04]	3890	1			T1	8		T3	5		T5	12
valid_sources[0x05]	3468	1			T1	1		T3	1		T5	27
valid_sources[0x06]	3471	1			T1	4		T5	12		T7	11
valid_sources[0x07]	3711	1			T1	1		T2	39		T3	2
valid_sources[0x08]	3284	1			T1	9		T3	22		T5	14
valid_sources[0x09]	4169	1			T1	8		T5	17		T6	21
valid_sources[0x0a]	4011	1			T1	6		T3	1		T5	17
valid_sources[0x0b]	3404	1			T1	9		T2	1		T3	9
valid_sources[0x0c]	6574	1			T1	8		T5	5		T7	13
valid_sources[0x0d]	4035	1			T1	2		T5	4		T7	18
valid_sources[0x0e]	3753	1			T1	7		T5	17		T7	9
valid_sources[0x0f]	2896	1			T1	2		T5	15		T7	11
valid_sources[0x10]	3700	1			T5	13		T7	9		T11	2
valid_sources[0x11]	3479	1			T5	10		T7	9		T12	34
valid_sources[0x12]	3799	1			T1	9		T5	9		T7	12
valid_sources[0x13]	3911	1			T1	2		T3	33		T5	23
valid_sources[0x14]	2943	1			T1	5		T3	3		T5	7
valid_sources[0x15]	3362	1			T1	4		T5	23		T6	1
valid_sources[0x16]	3178	1			T1	5		T5	10		T7	14
valid_sources[0x17]	3455	1			T1	11		T5	16		T7	9
valid_sources[0x18]	4140	1			T1	6		T3	1		T5	8
valid_sources[0x19]	7054	1			T1	1		T3	5		T5	12
valid_sources[0x1a]	4016	1			T1	1		T3	12		T5	11
valid_sources[0x1b]	3179	1			T1	5		T2	5		T3	10
valid_sources[0x1c]	2968	1			T1	1		T2	16		T5	9
valid_sources[0x1d]	3416	1			T1	3		T2	3		T3	31
valid_sources[0x1e]	3917	1			T1	1		T2	1		T5	8
valid_sources[0x1f]	3074	1			T1	3		T5	20		T7	12
valid_sources[0x20]	3350	1			T1	5		T3	2		T5	28
valid_sources[0x21]	4163	1			T1	2		T5	26		T7	11
valid_sources[0x22]	4039	1			T1	3		T5	19		T7	11
valid_sources[0x23]	5631	1			T2	1		T5	13		T7	5
valid_sources[0x24]	4289	1			T1	4		T5	16		T7	10
valid_sources[0x25]	3753	1			T1	12		T3	9		T5	7
valid_sources[0x26]	3206	1			T1	8		T5	9		T7	11
valid_sources[0x27]	3007	1			T1	6		T5	18		T7	10
valid_sources[0x28]	2934	1			T1	8		T5	8		T7	17
valid_sources[0x29]	3233	1			T1	8		T3	32		T5	18
valid_sources[0x2a]	3701	1			T1	8		T3	6		T5	13
valid_sources[0x2b]	2841	1			T1	13		T5	15		T7	7
valid_sources[0x2c]	3391	1			T1	1		T3	15		T5	20
valid_sources[0x2d]	3091	1			T1	4		T5	6		T7	12
valid_sources[0x2e]	2918	1			T1	6		T5	9		T7	11
valid_sources[0x2f]	3908	1			T1	3		T5	10		T6	23
valid_sources[0x30]	3347	1			T1	10		T5	13		T7	11
valid_sources[0x31]	4405	1			T1	3		T5	15		T7	6
valid_sources[0x32]	3898	1			T5	6		T7	9		T11	1
valid_sources[0x33]	3613	1			T1	11		T3	3		T5	17
valid_sources[0x34]	3900	1			T1	3		T5	15		T7	8
valid_sources[0x35]	3062	1			T1	1		T5	13		T7	20
valid_sources[0x36]	4444	1			T1	6		T5	16		T7	3
valid_sources[0x37]	3652	1			T1	3		T5	13		T7	16
valid_sources[0x38]	4291	1			T1	4		T5	18		T7	11
valid_sources[0x39]	3018	1			T1	4		T5	14		T7	10
valid_sources[0x3a]	3825	1			T1	4		T5	19		T7	4
valid_sources[0x3b]	3367	1			T1	8		T5	6		T7	9
valid_sources[0x3c]	3858	1			T1	1		T5	11		T7	9
valid_sources[0x3d]	4046	1			T1	2		T2	4		T5	9
valid_sources[0x3e]	7031	1			T1	4		T2	2		T3	1
valid_sources[0x3f]	4334	1			T1	4		T5	7		T7	12
valid_sources[0x40]	4562	1			T1	2		T3	4		T5	25
valid_sources[0x41]	3450	1			T1	4		T3	1		T5	19
valid_sources[0x42]	3575	1			T1	4		T2	1		T5	12
valid_sources[0x43]	3577	1			T1	2		T5	11		T7	14
valid_sources[0x44]	4163	1			T1	7		T5	11		T7	10
valid_sources[0x45]	3556	1			T5	4		T7	12		T11	1
valid_sources[0x46]	3869	1			T1	2		T2	7		T5	10
valid_sources[0x47]	3261	1			T5	13		T7	7		T11	4
valid_sources[0x48]	3580	1			T1	10		T3	7		T5	12
valid_sources[0x49]	3318	1			T1	7		T3	4		T5	28
valid_sources[0x4a]	5456	1			T1	6		T5	12		T7	16
valid_sources[0x4b]	6170	1			T1	3		T5	20		T7	6
valid_sources[0x4c]	3259	1			T1	1		T5	13		T7	14
valid_sources[0x4d]	3342	1			T1	3		T5	15		T7	9
valid_sources[0x4e]	6673	1			T1	5		T5	13		T7	11
valid_sources[0x4f]	3482	1			T1	2		T5	6		T7	13
valid_sources[0x50]	3180	1			T1	2		T3	1		T5	15
valid_sources[0x51]	3580	1			T1	11		T5	7		T6	13
valid_sources[0x52]	7140	1			T1	2		T2	1		T5	12
valid_sources[0x53]	3511	1			T1	4		T5	18		T7	16
valid_sources[0x54]	3276	1			T1	6		T3	20		T5	10
valid_sources[0x55]	3759	1			T1	3		T3	51		T5	20
valid_sources[0x56]	3164	1			T1	2		T3	9		T5	5
valid_sources[0x57]	3360	1			T1	2		T5	12		T7	17
valid_sources[0x58]	4038	1			T1	3		T5	1		T7	18
valid_sources[0x59]	2947	1			T1	6		T3	13		T5	10
valid_sources[0x5a]	4462	1			T1	7		T5	13		T7	10
valid_sources[0x5b]	3162	1			T1	7		T5	10		T7	3
valid_sources[0x5c]	3444	1			T1	2		T5	11		T7	22
valid_sources[0x5d]	4279	1			T1	5		T3	45		T5	15
valid_sources[0x5e]	6371	1			T1	1		T3	4		T5	14
valid_sources[0x5f]	3594	1			T1	3		T2	2		T3	1
valid_sources[0x60]	2872	1			T1	2		T5	6		T7	17
valid_sources[0x61]	6650	1			T1	1		T5	17		T7	11
valid_sources[0x62]	3881	1			T1	1		T3	5		T5	11
valid_sources[0x63]	4266	1			T1	1		T5	6		T6	18
valid_sources[0x64]	6023	1			T1	1		T5	21		T7	12
valid_sources[0x65]	3349	1			T1	5		T3	21		T5	12
valid_sources[0x66]	3305	1			T1	2		T2	1		T3	27
valid_sources[0x67]	3538	1			T1	8		T2	9		T5	20
valid_sources[0x68]	3386	1			T1	5		T5	14		T7	14
valid_sources[0x69]	3914	1			T5	3		T7	20		T11	1
valid_sources[0x6a]	2728	1			T5	11		T7	18		T12	33
valid_sources[0x6b]	3175	1			T1	2		T5	15		T7	10
valid_sources[0x6c]	4416	1			T1	5		T3	23		T5	2
valid_sources[0x6d]	3198	1			T1	4		T3	6		T5	8
valid_sources[0x6e]	3471	1			T4	212		T5	15		T7	9
valid_sources[0x6f]	3977	1			T1	6		T5	13		T7	10
valid_sources[0x70]	3160	1			T1	5		T5	9		T7	11
valid_sources[0x71]	3263	1			T1	5		T2	4		T5	6
valid_sources[0x72]	3256	1			T1	2		T2	1		T5	27
valid_sources[0x73]	3537	1			T1	7		T3	18		T5	8
valid_sources[0x74]	3646	1			T1	2		T2	6		T5	15
valid_sources[0x75]	4138	1			T1	5		T5	6		T7	11
valid_sources[0x76]	4032	1			T1	4		T5	12		T7	9
valid_sources[0x77]	3453	1			T1	3		T5	4		T7	4
valid_sources[0x78]	4103	1			T5	7		T7	19		T12	32
valid_sources[0x79]	3560	1			T1	5		T5	10		T7	8
valid_sources[0x7a]	3588	1			T1	1		T5	26		T7	5
valid_sources[0x7b]	4045	1			T1	4		T5	17		T7	12
valid_sources[0x7c]	3113	1			T1	5		T2	6		T3	3
valid_sources[0x7d]	3095	1			T1	1		T3	30		T5	17
valid_sources[0x7e]	3562	1			T1	4		T5	7		T7	17
valid_sources[0x7f]	3472	1			T1	1		T2	3		T5	5
valid_sources[0x80]	4347	1			T1	1		T5	11		T7	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

243456

1

T1

274

T2

39

T3

223

values[0x0]

all_enables

biggest_size

79629

1

T1

86

T2

17

T3

50

values[0x1]

all_enables

biggest_size

42871

1

T1

39

T2

8

T3

29