Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T6,T7,T12
1	0	Covered	T7,T12,T13

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55825620	9360	0	0
CascadeEffAonToRstPorAboveRise_A	55825620	9360	0	0
CascadeEffAonToRstPorIoAboveFall_A	53591119	9360	0	0
CascadeEffAonToRstPorIoAboveRise_A	53591119	9360	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26796491	9360	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26796491	9360	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13397909	9360	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13397909	9360	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26796638	9360	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26796638	9360	0	0
CascadeLcToLcAboveFall_A	55825620	22315	0	0
CascadeLcToLcAboveRise_A	55825620	22315	0	0
CascadeLcToLcAonAboveFall_A	1691058	22315	0	0
CascadeLcToLcAonAboveRise_A	1691058	22315	0	0
CascadeLcToLcShadowedAboveFall_A	55825620	22315	0	0
CascadeLcToLcShadowedAboveRise_A	55825620	22315	0	0
CascadePorToAonAboveFall_A	1691058	7642	0	0
CascadeSysToSysAboveFall_A	55825620	22315	0	0
CascadeSysToSysAboveRise_A	55825620	22315	0	0
ScanRstToAonRise_A	1691058	228	0	0
StablePorToAonRise_A	1691058	9360	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11933661	22315	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11933661	22315	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11933661	22315	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11933661	22315	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13397909	22315	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13397909	22315	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11933661	22315	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11933661	22315	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11933661	22315	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11933661	22315	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55825620	9360	0	0
T1	13564	1	0	0
T2	15541	2	0	0
T3	42502	1	0	0
T4	14969	2	0	0
T5	188484	27	0	0
T6	11380	2	0	0
T7	161205	21	0	0
T8	9551	1	0	0
T9	17074	2	0	0
T10	12937	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55825620	9360	0	0
T1	13564	1	0	0
T2	15541	2	0	0
T3	42502	1	0	0
T4	14969	2	0	0
T5	188484	27	0	0
T6	11380	2	0	0
T7	161205	21	0	0
T8	9551	1	0	0
T9	17074	2	0	0
T10	12937	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53591119	9360	0	0
T1	13020	1	0	0
T2	14928	2	0	0
T3	40801	1	0	0
T4	14371	2	0	0
T5	180904	27	0	0
T6	10916	2	0	0
T7	154762	21	0	0
T8	9169	1	0	0
T9	16391	2	0	0
T10	12419	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53591119	9360	0	0
T1	13020	1	0	0
T2	14928	2	0	0
T3	40801	1	0	0
T4	14371	2	0	0
T5	180904	27	0	0
T6	10916	2	0	0
T7	154762	21	0	0
T8	9169	1	0	0
T9	16391	2	0	0
T10	12419	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796491	9360	0	0
T1	6509	1	0	0
T2	7462	2	0	0
T3	20401	1	0	0
T4	7186	2	0	0
T5	90480	27	0	0
T6	5459	2	0	0
T7	77381	21	0	0
T8	4584	1	0	0
T9	8197	2	0	0
T10	6208	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796491	9360	0	0
T1	6509	1	0	0
T2	7462	2	0	0
T3	20401	1	0	0
T4	7186	2	0	0
T5	90480	27	0	0
T6	5459	2	0	0
T7	77381	21	0	0
T8	4584	1	0	0
T9	8197	2	0	0
T10	6208	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	9360	0	0
T1	3254	1	0	0
T2	3731	2	0	0
T3	10200	1	0	0
T4	3591	2	0	0
T5	45247	27	0	0
T6	2729	2	0	0
T7	38685	21	0	0
T8	2291	1	0	0
T9	4097	2	0	0
T10	3103	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	9360	0	0
T1	3254	1	0	0
T2	3731	2	0	0
T3	10200	1	0	0
T4	3591	2	0	0
T5	45247	27	0	0
T6	2729	2	0	0
T7	38685	21	0	0
T8	2291	1	0	0
T9	4097	2	0	0
T10	3103	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796638	9360	0	0
T1	6510	1	0	0
T2	7460	2	0	0
T3	20400	1	0	0
T4	7188	2	0	0
T5	90463	27	0	0
T6	5458	2	0	0
T7	77383	21	0	0
T8	4583	1	0	0
T9	8196	2	0	0
T10	6208	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796638	9360	0	0
T1	6510	1	0	0
T2	7460	2	0	0
T3	20400	1	0	0
T4	7188	2	0	0
T5	90463	27	0	0
T6	5458	2	0	0
T7	77383	21	0	0
T8	4583	1	0	0
T9	8196	2	0	0
T10	6208	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55825620	22315	0	0
T1	13564	1	0	0
T2	15541	6	0	0
T3	42502	1	0	0
T4	14969	6	0	0
T5	188484	102	0	0
T6	11380	6	0	0
T7	161205	60	0	0
T8	9551	1	0	0
T9	17074	2	0	0
T10	12937	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55825620	22315	0	0
T1	13564	1	0	0
T2	15541	6	0	0
T3	42502	1	0	0
T4	14969	6	0	0
T5	188484	102	0	0
T6	11380	6	0	0
T7	161205	60	0	0
T8	9551	1	0	0
T9	17074	2	0	0
T10	12937	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1691058	22315	0	0
T1	406	1	0	0
T2	466	6	0	0
T3	1273	1	0	0
T4	448	6	0	0
T5	5669	102	0	0
T6	339	6	0	0
T7	4910	60	0	0
T8	285	1	0	0
T9	511	2	0	0
T10	386	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1691058	22315	0	0
T1	406	1	0	0
T2	466	6	0	0
T3	1273	1	0	0
T4	448	6	0	0
T5	5669	102	0	0
T6	339	6	0	0
T7	4910	60	0	0
T8	285	1	0	0
T9	511	2	0	0
T10	386	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55825620	22315	0	0
T1	13564	1	0	0
T2	15541	6	0	0
T3	42502	1	0	0
T4	14969	6	0	0
T5	188484	102	0	0
T6	11380	6	0	0
T7	161205	60	0	0
T8	9551	1	0	0
T9	17074	2	0	0
T10	12937	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55825620	22315	0	0
T1	13564	1	0	0
T2	15541	6	0	0
T3	42502	1	0	0
T4	14969	6	0	0
T5	188484	102	0	0
T6	11380	6	0	0
T7	161205	60	0	0
T8	9551	1	0	0
T9	17074	2	0	0
T10	12937	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1691058	7642	0	0
T1	406	1	0	0
T2	466	1	0	0
T3	1273	1	0	0
T4	448	1	0	0
T5	5669	27	0	0
T6	339	1	0	0
T7	4910	12	0	0
T8	285	1	0	0
T9	511	9	0	0
T10	386	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55825620	22315	0	0
T1	13564	1	0	0
T2	15541	6	0	0
T3	42502	1	0	0
T4	14969	6	0	0
T5	188484	102	0	0
T6	11380	6	0	0
T7	161205	60	0	0
T8	9551	1	0	0
T9	17074	2	0	0
T10	12937	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55825620	22315	0	0
T1	13564	1	0	0
T2	15541	6	0	0
T3	42502	1	0	0
T4	14969	6	0	0
T5	188484	102	0	0
T6	11380	6	0	0
T7	161205	60	0	0
T8	9551	1	0	0
T9	17074	2	0	0
T10	12937	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1691058	228	0	0
T6	339	1	0	0
T7	4910	1	0	0
T8	285	0	0	0
T9	511	0	0	0
T10	386	0	0	0
T11	704	0	0	0
T12	14111	5	0	0
T13	2352	0	0	0
T23	455	0	0	0
T24	1231	0	0	0
T49	0	2	0	0
T50	0	8	0	0
T94	0	4	0	0
T95	0	1	0	0
T96	0	2	0	0
T100	0	1	0	0
T126	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1691058	9360	0	0
T1	406	1	0	0
T2	466	2	0	0
T3	1273	1	0	0
T4	448	2	0	0
T5	5669	27	0	0
T6	339	2	0	0
T7	4910	21	0	0
T8	285	1	0	0
T9	511	2	0	0
T10	386	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11933661	22315	0	0
T1	3236	1	0	0
T2	3537	6	0	0
T3	10157	1	0	0
T4	3494	6	0	0
T5	42128	102	0	0
T6	2342	6	0	0
T7	33611	60	0	0
T8	2225	1	0	0
T9	3983	2	0	0
T10	2678	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11933661	22315	0	0
T1	3236	1	0	0
T2	3537	6	0	0
T3	10157	1	0	0
T4	3494	6	0	0
T5	42128	102	0	0
T6	2342	6	0	0
T7	33611	60	0	0
T8	2225	1	0	0
T9	3983	2	0	0
T10	2678	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11933661	22315	0	0
T1	3236	1	0	0
T2	3537	6	0	0
T3	10157	1	0	0
T4	3494	6	0	0
T5	42128	102	0	0
T6	2342	6	0	0
T7	33611	60	0	0
T8	2225	1	0	0
T9	3983	2	0	0
T10	2678	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11933661	22315	0	0
T1	3236	1	0	0
T2	3537	6	0	0
T3	10157	1	0	0
T4	3494	6	0	0
T5	42128	102	0	0
T6	2342	6	0	0
T7	33611	60	0	0
T8	2225	1	0	0
T9	3983	2	0	0
T10	2678	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	22315	0	0
T1	3254	1	0	0
T2	3731	6	0	0
T3	10200	1	0	0
T4	3591	6	0	0
T5	45247	102	0	0
T6	2729	6	0	0
T7	38685	60	0	0
T8	2291	1	0	0
T9	4097	2	0	0
T10	3103	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	22315	0	0
T1	3254	1	0	0
T2	3731	6	0	0
T3	10200	1	0	0
T4	3591	6	0	0
T5	45247	102	0	0
T6	2729	6	0	0
T7	38685	60	0	0
T8	2291	1	0	0
T9	4097	2	0	0
T10	3103	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11933661	22315	0	0
T1	3236	1	0	0
T2	3537	6	0	0
T3	10157	1	0	0
T4	3494	6	0	0
T5	42128	102	0	0
T6	2342	6	0	0
T7	33611	60	0	0
T8	2225	1	0	0
T9	3983	2	0	0
T10	2678	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11933661	22315	0	0
T1	3236	1	0	0
T2	3537	6	0	0
T3	10157	1	0	0
T4	3494	6	0	0
T5	42128	102	0	0
T6	2342	6	0	0
T7	33611	60	0	0
T8	2225	1	0	0
T9	3983	2	0	0
T10	2678	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11933661	22315	0	0
T1	3236	1	0	0
T2	3537	6	0	0
T3	10157	1	0	0
T4	3494	6	0	0
T5	42128	102	0	0
T6	2342	6	0	0
T7	33611	60	0	0
T8	2225	1	0	0
T9	3983	2	0	0
T10	2678	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11933661	22315	0	0
T1	3236	1	0	0
T2	3537	6	0	0
T3	10157	1	0	0
T4	3494	6	0	0
T5	42128	102	0	0
T6	2342	6	0	0
T7	33611	60	0	0
T8	2225	1	0	0
T9	3983	2	0	0
T10	2678	6	0	0