Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T10
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T12
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T12
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T12
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T12
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T12
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T12
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T12
1	0	Covered	T2,T4,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13397909	13889	0	0
gen_assertions[0].RstEnOn_A	13397909	1129	0	0
gen_assertions[0].RstNOff_A	13397909	13889	0	0
gen_assertions[0].RstNOn_A	13397909	1129	0	0
gen_assertions[1].RstEnOff_A	53591119	12560	0	0
gen_assertions[1].RstEnOn_A	53591119	1096	0	0
gen_assertions[1].RstNOff_A	53591119	12560	0	0
gen_assertions[1].RstNOn_A	53591119	1096	0	0
gen_assertions[2].RstEnOff_A	26796491	12602	0	0
gen_assertions[2].RstEnOn_A	26796491	1064	0	0
gen_assertions[2].RstNOff_A	26796491	12602	0	0
gen_assertions[2].RstNOn_A	26796491	1064	0	0
gen_assertions[3].RstEnOff_A	26796638	12666	0	0
gen_assertions[3].RstEnOn_A	26796638	1127	0	0
gen_assertions[3].RstNOff_A	26796638	12666	0	0
gen_assertions[3].RstNOn_A	26796638	1127	0	0
gen_assertions[4].RstEnOff_A	1691058	22135	0	0
gen_assertions[4].RstEnOn_A	1691058	1169	0	0
gen_assertions[4].RstNOff_A	1691058	22135	0	0
gen_assertions[4].RstNOn_A	1691058	1169	0	0
gen_assertions[5].RstEnOff_A	13397909	14104	0	0
gen_assertions[5].RstEnOn_A	13397909	1195	0	0
gen_assertions[5].RstNOff_A	13397909	14104	0	0
gen_assertions[5].RstNOn_A	13397909	1195	0	0
gen_assertions[6].RstEnOff_A	13397909	14156	0	0
gen_assertions[6].RstEnOn_A	13397909	1248	0	0
gen_assertions[6].RstNOff_A	13397909	14156	0	0
gen_assertions[6].RstNOn_A	13397909	1248	0	0
gen_assertions[7].RstEnOff_A	13397909	14213	0	0
gen_assertions[7].RstEnOn_A	13397909	1301	0	0
gen_assertions[7].RstNOff_A	13397909	14213	0	0
gen_assertions[7].RstNOn_A	13397909	1301	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	13889	0	0
T1	3254	6	0	0
T2	3731	4	0	0
T3	10200	3	0	0
T4	3591	4	0	0
T5	45247	75	0	0
T6	2729	4	0	0
T7	38685	39	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	5	0	0
T11	0	20	0	0
T12	0	122	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	1129	0	0
T1	3254	6	0	0
T2	3731	0	0	0
T3	10200	3	0	0
T4	3591	0	0	0
T5	45247	0	0	0
T6	2729	0	0	0
T7	38685	0	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	2	0	0
T11	0	2	0	0
T12	0	6	0	0
T23	0	3	0	0
T24	0	12	0	0
T47	0	1	0	0
T49	0	23	0	0
T81	0	4	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	13889	0	0
T1	3254	6	0	0
T2	3731	4	0	0
T3	10200	3	0	0
T4	3591	4	0	0
T5	45247	75	0	0
T6	2729	4	0	0
T7	38685	39	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	5	0	0
T11	0	20	0	0
T12	0	122	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	1129	0	0
T1	3254	6	0	0
T2	3731	0	0	0
T3	10200	3	0	0
T4	3591	0	0	0
T5	45247	0	0	0
T6	2729	0	0	0
T7	38685	0	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	2	0	0
T11	0	2	0	0
T12	0	6	0	0
T23	0	3	0	0
T24	0	12	0	0
T47	0	1	0	0
T49	0	23	0	0
T81	0	4	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53591119	12560	0	0
T1	13020	7	0	0
T2	14928	4	0	0
T3	40801	4	0	0
T4	14371	4	0	0
T5	180904	68	0	0
T6	10916	4	0	0
T7	154762	34	0	0
T8	9169	0	0	0
T9	16391	0	0	0
T10	12419	5	0	0
T11	0	20	0	0
T12	0	112	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53591119	1096	0	0
T1	13020	7	0	0
T2	14928	0	0	0
T3	40801	4	0	0
T4	14371	0	0	0
T5	180904	0	0	0
T6	10916	0	0	0
T7	154762	0	0	0
T8	9169	0	0	0
T9	16391	0	0	0
T10	12419	0	0	0
T12	0	8	0	0
T23	0	7	0	0
T24	0	17	0	0
T49	0	21	0	0
T50	0	24	0	0
T51	0	1	0	0
T81	0	5	0	0
T82	0	6	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53591119	12560	0	0
T1	13020	7	0	0
T2	14928	4	0	0
T3	40801	4	0	0
T4	14371	4	0	0
T5	180904	68	0	0
T6	10916	4	0	0
T7	154762	34	0	0
T8	9169	0	0	0
T9	16391	0	0	0
T10	12419	5	0	0
T11	0	20	0	0
T12	0	112	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53591119	1096	0	0
T1	13020	7	0	0
T2	14928	0	0	0
T3	40801	4	0	0
T4	14371	0	0	0
T5	180904	0	0	0
T6	10916	0	0	0
T7	154762	0	0	0
T8	9169	0	0	0
T9	16391	0	0	0
T10	12419	0	0	0
T12	0	8	0	0
T23	0	7	0	0
T24	0	17	0	0
T49	0	21	0	0
T50	0	24	0	0
T51	0	1	0	0
T81	0	5	0	0
T82	0	6	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796491	12602	0	0
T1	6509	8	0	0
T2	7462	4	0	0
T3	20401	5	0	0
T4	7186	4	0	0
T5	90480	68	0	0
T6	5459	4	0	0
T7	77381	34	0	0
T8	4584	0	0	0
T9	8197	0	0	0
T10	6208	5	0	0
T11	0	20	0	0
T12	0	110	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796491	1064	0	0
T1	6509	8	0	0
T2	7462	0	0	0
T3	20401	5	0	0
T4	7186	0	0	0
T5	90480	0	0	0
T6	5459	0	0	0
T7	77381	0	0	0
T8	4584	0	0	0
T9	8197	0	0	0
T10	6208	0	0	0
T12	0	6	0	0
T23	0	10	0	0
T24	0	12	0	0
T47	0	1	0	0
T49	0	20	0	0
T50	0	17	0	0
T80	0	1	0	0
T81	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796491	12602	0	0
T1	6509	8	0	0
T2	7462	4	0	0
T3	20401	5	0	0
T4	7186	4	0	0
T5	90480	68	0	0
T6	5459	4	0	0
T7	77381	34	0	0
T8	4584	0	0	0
T9	8197	0	0	0
T10	6208	5	0	0
T11	0	20	0	0
T12	0	110	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796491	1064	0	0
T1	6509	8	0	0
T2	7462	0	0	0
T3	20401	5	0	0
T4	7186	0	0	0
T5	90480	0	0	0
T6	5459	0	0	0
T7	77381	0	0	0
T8	4584	0	0	0
T9	8197	0	0	0
T10	6208	0	0	0
T12	0	6	0	0
T23	0	10	0	0
T24	0	12	0	0
T47	0	1	0	0
T49	0	20	0	0
T50	0	17	0	0
T80	0	1	0	0
T81	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796638	12666	0	0
T1	6510	9	0	0
T2	7460	4	0	0
T3	20400	5	0	0
T4	7188	4	0	0
T5	90463	68	0	0
T6	5458	4	0	0
T7	77383	34	0	0
T8	4583	0	0	0
T9	8196	0	0	0
T10	6208	5	0	0
T11	0	20	0	0
T12	0	113	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796638	1127	0	0
T1	6510	9	0	0
T2	7460	0	0	0
T3	20400	5	0	0
T4	7188	0	0	0
T5	90463	0	0	0
T6	5458	0	0	0
T7	77383	0	0	0
T8	4583	0	0	0
T9	8196	0	0	0
T10	6208	0	0	0
T12	0	9	0	0
T23	0	9	0	0
T24	0	12	0	0
T26	0	1	0	0
T49	0	24	0	0
T50	0	21	0	0
T82	0	10	0	0
T83	0	6	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796638	12666	0	0
T1	6510	9	0	0
T2	7460	4	0	0
T3	20400	5	0	0
T4	7188	4	0	0
T5	90463	68	0	0
T6	5458	4	0	0
T7	77383	34	0	0
T8	4583	0	0	0
T9	8196	0	0	0
T10	6208	5	0	0
T11	0	20	0	0
T12	0	113	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26796638	1127	0	0
T1	6510	9	0	0
T2	7460	0	0	0
T3	20400	5	0	0
T4	7188	0	0	0
T5	90463	0	0	0
T6	5458	0	0	0
T7	77383	0	0	0
T8	4583	0	0	0
T9	8196	0	0	0
T10	6208	0	0	0
T12	0	9	0	0
T23	0	9	0	0
T24	0	12	0	0
T26	0	1	0	0
T49	0	24	0	0
T50	0	21	0	0
T82	0	10	0	0
T83	0	6	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1691058	22135	0	0
T1	406	9	0	0
T2	466	6	0	0
T3	1273	8	0	0
T4	448	6	0	0
T5	5669	92	0	0
T6	339	5	0	0
T7	4910	60	0	0
T8	285	1	0	0
T9	511	2	0	0
T10	386	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1691058	1169	0	0
T1	406	8	0	0
T2	466	0	0	0
T3	1273	7	0	0
T4	448	0	0	0
T5	5669	0	0	0
T6	339	0	0	0
T7	4910	0	0	0
T8	285	0	0	0
T9	511	0	0	0
T10	386	0	0	0
T12	0	7	0	0
T23	0	12	0	0
T24	0	9	0	0
T49	0	24	0	0
T50	0	25	0	0
T82	0	10	0	0
T83	0	8	0	0
T84	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1691058	22135	0	0
T1	406	9	0	0
T2	466	6	0	0
T3	1273	8	0	0
T4	448	6	0	0
T5	5669	92	0	0
T6	339	5	0	0
T7	4910	60	0	0
T8	285	1	0	0
T9	511	2	0	0
T10	386	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1691058	1169	0	0
T1	406	8	0	0
T2	466	0	0	0
T3	1273	7	0	0
T4	448	0	0	0
T5	5669	0	0	0
T6	339	0	0	0
T7	4910	0	0	0
T8	285	0	0	0
T9	511	0	0	0
T10	386	0	0	0
T12	0	7	0	0
T23	0	12	0	0
T24	0	9	0	0
T49	0	24	0	0
T50	0	25	0	0
T82	0	10	0	0
T83	0	8	0	0
T84	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	14104	0	0
T1	3254	11	0	0
T2	3731	4	0	0
T3	10200	8	0	0
T4	3591	4	0	0
T5	45247	75	0	0
T6	2729	4	0	0
T7	38685	39	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	5	0	0
T11	0	20	0	0
T12	0	123	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	1195	0	0
T1	3254	11	0	0
T2	3731	0	0	0
T3	10200	8	0	0
T4	3591	0	0	0
T5	45247	0	0	0
T6	2729	0	0	0
T7	38685	0	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	0	0	0
T12	0	7	0	0
T23	0	12	0	0
T24	0	13	0	0
T26	0	1	0	0
T49	0	21	0	0
T50	0	20	0	0
T82	0	9	0	0
T83	0	5	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	14104	0	0
T1	3254	11	0	0
T2	3731	4	0	0
T3	10200	8	0	0
T4	3591	4	0	0
T5	45247	75	0	0
T6	2729	4	0	0
T7	38685	39	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	5	0	0
T11	0	20	0	0
T12	0	123	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	1195	0	0
T1	3254	11	0	0
T2	3731	0	0	0
T3	10200	8	0	0
T4	3591	0	0	0
T5	45247	0	0	0
T6	2729	0	0	0
T7	38685	0	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	0	0	0
T12	0	7	0	0
T23	0	12	0	0
T24	0	13	0	0
T26	0	1	0	0
T49	0	21	0	0
T50	0	20	0	0
T82	0	9	0	0
T83	0	5	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	14156	0	0
T1	3254	10	0	0
T2	3731	4	0	0
T3	10200	10	0	0
T4	3591	4	0	0
T5	45247	75	0	0
T6	2729	4	0	0
T7	38685	39	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	5	0	0
T11	0	20	0	0
T12	0	125	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	1248	0	0
T1	3254	10	0	0
T2	3731	0	0	0
T3	10200	10	0	0
T4	3591	0	0	0
T5	45247	0	0	0
T6	2729	0	0	0
T7	38685	0	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	0	0	0
T12	0	9	0	0
T23	0	10	0	0
T24	0	11	0	0
T49	0	19	0	0
T50	0	17	0	0
T80	0	1	0	0
T82	0	12	0	0
T83	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	14156	0	0
T1	3254	10	0	0
T2	3731	4	0	0
T3	10200	10	0	0
T4	3591	4	0	0
T5	45247	75	0	0
T6	2729	4	0	0
T7	38685	39	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	5	0	0
T11	0	20	0	0
T12	0	125	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	1248	0	0
T1	3254	10	0	0
T2	3731	0	0	0
T3	10200	10	0	0
T4	3591	0	0	0
T5	45247	0	0	0
T6	2729	0	0	0
T7	38685	0	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	0	0	0
T12	0	9	0	0
T23	0	10	0	0
T24	0	11	0	0
T49	0	19	0	0
T50	0	17	0	0
T80	0	1	0	0
T82	0	12	0	0
T83	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	14213	0	0
T1	3254	13	0	0
T2	3731	4	0	0
T3	10200	11	0	0
T4	3591	4	0	0
T5	45247	75	0	0
T6	2729	4	0	0
T7	38685	39	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	5	0	0
T11	0	20	0	0
T12	0	123	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	1301	0	0
T1	3254	13	0	0
T2	3731	0	0	0
T3	10200	11	0	0
T4	3591	0	0	0
T5	45247	0	0	0
T6	2729	0	0	0
T7	38685	0	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	0	0	0
T12	0	7	0	0
T23	0	13	0	0
T24	0	12	0	0
T49	0	24	0	0
T50	0	16	0	0
T82	0	13	0	0
T83	0	8	0	0
T84	0	11	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	14213	0	0
T1	3254	13	0	0
T2	3731	4	0	0
T3	10200	11	0	0
T4	3591	4	0	0
T5	45247	75	0	0
T6	2729	4	0	0
T7	38685	39	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	5	0	0
T11	0	20	0	0
T12	0	123	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13397909	1301	0	0
T1	3254	13	0	0
T2	3731	0	0	0
T3	10200	11	0	0
T4	3591	0	0	0
T5	45247	0	0	0
T6	2729	0	0	0
T7	38685	0	0	0
T8	2291	0	0	0
T9	4097	0	0	0
T10	3103	0	0	0
T12	0	7	0	0
T23	0	13	0	0
T24	0	12	0	0
T49	0	24	0	0
T50	0	16	0	0
T82	0	13	0	0
T83	0	8	0	0
T84	0	11	0	0