Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12720798	8332	0	0
alert_regwen_rd_A	12720798	5158	0	0
cpu_regwen_rd_A	12720798	4984	0	0
sw_rst_ctrl_n_0_rd_A	12720798	9744	0	0
sw_rst_ctrl_n_1_rd_A	12720798	9755	0	0
sw_rst_ctrl_n_2_rd_A	12720798	9855	0	0
sw_rst_ctrl_n_3_rd_A	12720798	9519	0	0
sw_rst_ctrl_n_4_rd_A	12720798	9636	0	0
sw_rst_ctrl_n_5_rd_A	12720798	9702	0	0
sw_rst_ctrl_n_6_rd_A	12720798	9678	0	0
sw_rst_ctrl_n_7_rd_A	12720798	9826	0	0
sw_rst_regwen_0_rd_A	12720798	5370	0	0
sw_rst_regwen_1_rd_A	12720798	5352	0	0
sw_rst_regwen_2_rd_A	12720798	5415	0	0
sw_rst_regwen_3_rd_A	12720798	5345	0	0
sw_rst_regwen_4_rd_A	12720798	5235	0	0
sw_rst_regwen_5_rd_A	12720798	5247	0	0
sw_rst_regwen_6_rd_A	12720798	5328	0	0
sw_rst_regwen_7_rd_A	12720798	5284	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	8332	0	0
T59	11664	2	0	0
T61	3518	17	0	0
T62	2380	94	0	0
T63	7413	454	0	0
T64	9864	1	0	0
T65	11143	1	0	0
T85	4321	440	0	0
T86	9766	369	0	0
T87	13088	536	0	0
T92	9781	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	5158	0	0
T15	4416	0	0	0
T40	0	66	0	0
T46	0	59	0	0
T48	30661	52	0	0
T49	143613	136	0	0
T50	198264	0	0	0
T66	5762	0	0	0
T71	1601	0	0	0
T82	11762	0	0	0
T95	0	86	0	0
T97	0	80	0	0
T99	2380	0	0	0
T100	5844	0	0	0
T101	5609	0	0	0
T102	0	93	0	0
T103	0	71	0	0
T123	0	29	0	0
T124	0	63	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	4984	0	0
T15	4416	0	0	0
T40	0	47	0	0
T46	0	83	0	0
T48	30661	37	0	0
T49	143613	110	0	0
T50	198264	0	0	0
T66	5762	0	0	0
T71	1601	0	0	0
T82	11762	0	0	0
T95	0	95	0	0
T97	0	69	0	0
T99	2380	0	0	0
T100	5844	0	0	0
T101	5609	0	0	0
T102	0	90	0	0
T103	0	49	0	0
T123	0	2	0	0
T124	0	64	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	9744	0	0
T3	10157	171	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	10	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T48	0	30	0	0
T49	0	237	0	0
T82	0	182	0	0
T95	0	238	0	0
T99	0	13	0	0
T100	0	20	0	0
T101	0	72	0	0
T125	0	29	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	9755	0	0
T3	10157	143	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	14	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T48	0	36	0	0
T49	0	318	0	0
T82	0	180	0	0
T95	0	205	0	0
T99	0	17	0	0
T100	0	25	0	0
T101	0	69	0	0
T125	0	26	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	9855	0	0
T3	10157	162	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	19	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T48	0	42	0	0
T49	0	305	0	0
T82	0	230	0	0
T95	0	232	0	0
T99	0	27	0	0
T100	0	22	0	0
T101	0	67	0	0
T125	0	32	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	9519	0	0
T3	10157	148	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	20	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T48	0	53	0	0
T49	0	281	0	0
T82	0	173	0	0
T95	0	266	0	0
T99	0	13	0	0
T100	0	13	0	0
T101	0	63	0	0
T125	0	29	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	9636	0	0
T3	10157	125	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	19	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T48	0	39	0	0
T49	0	344	0	0
T82	0	154	0	0
T95	0	243	0	0
T99	0	18	0	0
T100	0	12	0	0
T101	0	84	0	0
T125	0	35	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	9702	0	0
T3	10157	143	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	15	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T48	0	54	0	0
T49	0	320	0	0
T82	0	172	0	0
T95	0	242	0	0
T99	0	11	0	0
T100	0	19	0	0
T101	0	71	0	0
T125	0	29	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	9678	0	0
T3	10157	140	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	15	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T48	0	50	0	0
T49	0	255	0	0
T82	0	207	0	0
T95	0	209	0	0
T99	0	15	0	0
T100	0	10	0	0
T101	0	80	0	0
T125	0	29	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	9826	0	0
T3	10157	143	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	15	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T48	0	61	0	0
T49	0	307	0	0
T82	0	203	0	0
T95	0	230	0	0
T99	0	19	0	0
T100	0	13	0	0
T101	0	64	0	0
T125	0	25	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	5370	0	0
T3	10157	28	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	0	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T40	0	48	0	0
T46	0	75	0	0
T48	0	53	0	0
T49	0	133	0	0
T82	0	21	0	0
T95	0	73	0	0
T97	0	84	0	0
T100	0	9	0	0
T102	0	69	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	5352	0	0
T3	10157	38	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	0	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T40	0	52	0	0
T46	0	89	0	0
T48	0	59	0	0
T49	0	128	0	0
T82	0	38	0	0
T95	0	104	0	0
T97	0	65	0	0
T100	0	10	0	0
T102	0	79	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	5415	0	0
T3	10157	19	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	0	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T40	0	50	0	0
T46	0	82	0	0
T48	0	54	0	0
T49	0	136	0	0
T82	0	26	0	0
T95	0	114	0	0
T97	0	52	0	0
T100	0	13	0	0
T102	0	101	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	5345	0	0
T3	10157	28	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	0	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T40	0	43	0	0
T46	0	69	0	0
T48	0	48	0	0
T49	0	138	0	0
T82	0	34	0	0
T95	0	101	0	0
T97	0	82	0	0
T100	0	2	0	0
T102	0	101	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	5235	0	0
T3	10157	31	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	0	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T40	0	39	0	0
T46	0	76	0	0
T48	0	51	0	0
T49	0	124	0	0
T82	0	17	0	0
T95	0	89	0	0
T97	0	90	0	0
T100	0	7	0	0
T102	0	73	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	5247	0	0
T3	10157	41	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	0	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T40	0	38	0	0
T46	0	83	0	0
T48	0	37	0	0
T49	0	137	0	0
T82	0	43	0	0
T95	0	96	0	0
T97	0	93	0	0
T100	0	8	0	0
T102	0	81	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	5328	0	0
T3	10157	26	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	0	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T40	0	63	0	0
T46	0	74	0	0
T48	0	50	0	0
T49	0	103	0	0
T82	0	38	0	0
T95	0	86	0	0
T97	0	64	0	0
T100	0	1	0	0
T102	0	83	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12720798	5284	0	0
T3	10157	30	0	0
T4	3494	0	0	0
T5	42128	0	0	0
T6	2342	0	0	0
T7	33611	0	0	0
T8	2225	0	0	0
T9	3983	0	0	0
T10	2678	0	0	0
T11	4419	0	0	0
T12	97233	0	0	0
T40	0	52	0	0
T46	0	90	0	0
T48	0	47	0	0
T49	0	141	0	0
T82	0	34	0	0
T95	0	95	0	0
T97	0	55	0	0
T100	0	6	0	0
T102	0	99	0	0