Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg

Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sw_rst_ctrl_n[0]	100.00	1	100	1	64	64
sw_rst_ctrl_n[1]	100.00	1	100	1	64	64
sw_rst_ctrl_n[2]	100.00	1	100	1	64	64
sw_rst_ctrl_n[3]	100.00	1	100	1	64	64
sw_rst_ctrl_n[4]	100.00	1	100	1	64	64
sw_rst_ctrl_n[5]	100.00	1	100	1	64	64
sw_rst_ctrl_n[6]	100.00	1	100	1	64	64
sw_rst_ctrl_n[7]	100.00	1	100	1	64	64

---

Group Instance : sw_rst_ctrl_n[0]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[0]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[0]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[0]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[1]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[1]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[1]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[1]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[2]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[2]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[2]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[2]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[3]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[3]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[3]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[3]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[4]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[4]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[4]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[4]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[5]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[5]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[5]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[5]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[6]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[6]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[6]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[6]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[7]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[7]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[7]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[7]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T7

32

T8

32

T47

32

auto[1]

4597

1

T1

3

T7

23

T8

7

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T7

32

T8

32

T47

32

auto[1]

4597

1

T1

3

T7

23

T8

7

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1789

1

T1

1

T7

15

T8

11

auto[1]

4408

1

T1

2

T7

40

T8

28

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1789

1

T1

1

T7

15

T8

11

auto[1]

4408

1

T1

2

T7

40

T8

28

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

400

1

T7

8

T8

8

T47

8

auto[0]

auto[1]

1200

1

T7

24

T8

24

T47

24

auto[1]

auto[0]

1389

1

T1

1

T7

7

T8

3

auto[1]

auto[1]

3208

1

T1

2

T7

16

T8

4

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1481

1

T1

3

T7

28

T8

28

auto[1]

4468

1

T7

27

T8

11

T47

24

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1481

1

T1

3

T7

28

T8

28

auto[1]

4468

1

T7

27

T8

11

T47

24

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1690

1

T1

2

T7

12

T8

9

auto[1]

4259

1

T1

1

T7

43

T8

30

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1690

1

T1

2

T7

12

T8

9

auto[1]

4259

1

T1

1

T7

43

T8

30

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

393

1

T1

2

T7

7

T8

7

auto[0]

auto[1]

1088

1

T1

1

T7

21

T8

21

auto[1]

auto[0]

1297

1

T7

5

T8

2

T47

8

auto[1]

auto[1]

3171

1

T7

22

T8

9

T47

16

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1272

1

T7

24

T8

24

T10

3

auto[1]

4575

1

T1

3

T7

31

T8

15

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1272

1

T7

24

T8

24

T10

3

auto[1]

4575

1

T1

3

T7

31

T8

15

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T7

15

T8

8

T10

1

auto[1]

4244

1

T1

3

T7

40

T8

31

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T7

15

T8

8

T10

1

auto[1]

4244

1

T1

3

T7

40

T8

31

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

335

1

T7

6

T8

6

T10

1

auto[0]

auto[1]

937

1

T7

18

T8

18

T10

2

auto[1]

auto[0]

1268

1

T7

9

T8

2

T47

9

auto[1]

auto[1]

3307

1

T1

3

T7

22

T8

13

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1069

1

T1

3

T7

20

T8

20

auto[1]

4762

1

T7

35

T8

19

T10

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1069

1

T1

3

T7

20

T8

20

auto[1]

4762

1

T7

35

T8

19

T10

3

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1642

1

T1

1

T7

14

T8

10

auto[1]

4189

1

T1

2

T7

41

T8

29

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1642

1

T1

1

T7

14

T8

10

auto[1]

4189

1

T1

2

T7

41

T8

29

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

282

1

T1

1

T7

5

T8

5

auto[0]

auto[1]

787

1

T1

2

T7

15

T8

15

auto[1]

auto[0]

1360

1

T7

9

T8

5

T47

11

auto[1]

auto[1]

3402

1

T7

26

T8

14

T10

3

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

896

1

T1

3

T7

16

T8

16

auto[1]

4935

1

T7

39

T8

23

T47

36

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

896

1

T1

3

T7

16

T8

16

auto[1]

4935

1

T7

39

T8

23

T47

36

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1613

1

T1

1

T7

18

T8

12

auto[1]

4218

1

T1

2

T7

37

T8

27

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1613

1

T1

1

T7

18

T8

12

auto[1]

4218

1

T1

2

T7

37

T8

27

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

243

1

T1

1

T7

4

T8

4

auto[0]

auto[1]

653

1

T1

2

T7

12

T8

12

auto[1]

auto[0]

1370

1

T7

14

T8

8

T47

10

auto[1]

auto[1]

3565

1

T7

25

T8

15

T47

26

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687

1

T7

12

T8

12

T47

12

auto[1]

5144

1

T1

3

T7

43

T8

27

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687

1

T7

12

T8

12

T47

12

auto[1]

5144

1

T1

3

T7

43

T8

27

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1608

1

T1

1

T7

15

T8

11

auto[1]

4223

1

T1

2

T7

40

T8

28

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1608

1

T1

1

T7

15

T8

11

auto[1]

4223

1

T1

2

T7

40

T8

28

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

192

1

T7

3

T8

3

T47

3

auto[0]

auto[1]

495

1

T7

9

T8

9

T47

9

auto[1]

auto[0]

1416

1

T1

1

T7

12

T8

8

auto[1]

auto[1]

3728

1

T1

2

T7

31

T8

19

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

478

1

T1

3

T7

8

T8

8

auto[1]

5353

1

T7

47

T8

31

T47

44

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

478

1

T1

3

T7

8

T8

8

auto[1]

5353

1

T7

47

T8

31

T47

44

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1607

1

T1

1

T7

18

T8

11

auto[1]

4224

1

T1

2

T7

37

T8

28

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1607

1

T1

1

T7

18

T8

11

auto[1]

4224

1

T1

2

T7

37

T8

28

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

136

1

T1

1

T7

2

T8

2

auto[0]

auto[1]

342

1

T1

2

T7

6

T8

6

auto[1]

auto[0]

1471

1

T7

16

T8

9

T47

13

auto[1]

auto[1]

3882

1

T7

31

T8

22

T47

31

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

281

1

T1

3

T7

4

T8

4

auto[1]

5550

1

T7

51

T8

35

T47

48

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

281

1

T1

3

T7

4

T8

4

auto[1]

5550

1

T7

51

T8

35

T47

48

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1673

1

T1

2

T7

15

T8

10

auto[1]

4158

1

T1

1

T7

40

T8

29

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1673

1

T1

2

T7

15

T8

10

auto[1]

4158

1

T1

1

T7

40

T8

29

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

88

1

T1

2

T7

1

T8

1

auto[0]

auto[1]

193

1

T1

1

T7

3

T8

3

auto[1]

auto[0]

1585

1

T7

14

T8

9

T47

12

auto[1]

auto[1]

3965

1

T7

37

T8

26

T47

36