Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	641247	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

384014

1

T1

144

T3

1054

T5

1102

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	547465	1			T1	186		T2	1		T3	1531
values[0x0]	239061	1			T1	107		T3	631		T5	847
values[0x1]	238735	1			T1	86		T3	638		T5	853

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	538283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

486978

1

T1

175

T3

1356

T5

1425

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3214	1			T1	3		T3	7		T5	5
valid_sources[0x01]	5333	1			T3	8		T6	9		T9	12
valid_sources[0x02]	5116	1			T3	11		T5	59		T6	8
valid_sources[0x03]	3726	1			T1	1		T3	10		T6	4
valid_sources[0x04]	3402	1			T3	9		T5	6		T6	2
valid_sources[0x05]	4369	1			T1	1		T3	9		T5	18
valid_sources[0x06]	4429	1			T1	1		T3	9		T5	39
valid_sources[0x07]	4622	1			T1	1		T3	7		T5	4
valid_sources[0x08]	3175	1			T3	8		T6	12		T9	10
valid_sources[0x09]	3996	1			T1	1		T3	9		T6	8
valid_sources[0x0a]	3413	1			T3	6		T6	4		T9	12
valid_sources[0x0b]	2984	1			T1	3		T3	9		T6	12
valid_sources[0x0c]	4301	1			T1	3		T3	8		T6	3
valid_sources[0x0d]	5806	1			T3	13		T5	22		T6	9
valid_sources[0x0e]	3295	1			T1	1		T3	9		T5	3
valid_sources[0x0f]	3968	1			T1	2		T3	6		T6	10
valid_sources[0x10]	3278	1			T3	9		T5	41		T6	11
valid_sources[0x11]	3245	1			T3	6		T6	7		T8	6
valid_sources[0x12]	3469	1			T1	1		T3	14		T6	6
valid_sources[0x13]	3694	1			T1	3		T3	16		T6	9
valid_sources[0x14]	3123	1			T1	1		T3	9		T6	5
valid_sources[0x15]	3708	1			T1	1		T3	6		T6	10
valid_sources[0x16]	3736	1			T3	11		T6	12		T9	9
valid_sources[0x17]	3161	1			T3	13		T5	49		T6	8
valid_sources[0x18]	3632	1			T1	2		T3	11		T6	13
valid_sources[0x19]	3383	1			T3	9		T5	12		T6	6
valid_sources[0x1a]	4117	1			T1	3		T3	13		T6	3
valid_sources[0x1b]	3773	1			T3	15		T5	135		T6	7
valid_sources[0x1c]	4063	1			T1	3		T3	15		T5	72
valid_sources[0x1d]	3312	1			T1	1		T3	13		T6	10
valid_sources[0x1e]	3459	1			T1	1		T3	9		T5	47
valid_sources[0x1f]	3432	1			T1	4		T3	9		T6	13
valid_sources[0x20]	3308	1			T3	22		T5	15		T6	5
valid_sources[0x21]	3479	1			T1	1		T3	8		T5	13
valid_sources[0x22]	3831	1			T3	8		T5	16		T6	10
valid_sources[0x23]	7470	1			T1	2		T3	11		T5	4
valid_sources[0x24]	4488	1			T1	5		T3	11		T6	5
valid_sources[0x25]	3934	1			T1	1		T3	8		T6	4
valid_sources[0x26]	4139	1			T1	2		T3	16		T6	6
valid_sources[0x27]	4045	1			T3	7		T5	105		T6	7
valid_sources[0x28]	3362	1			T3	6		T6	2		T9	9
valid_sources[0x29]	4722	1			T3	11		T5	34		T6	11
valid_sources[0x2a]	3249	1			T1	5		T3	11		T6	5
valid_sources[0x2b]	4037	1			T1	3		T3	6		T6	9
valid_sources[0x2c]	3697	1			T3	7		T5	6		T6	13
valid_sources[0x2d]	3291	1			T1	2		T3	12		T5	28
valid_sources[0x2e]	3729	1			T3	12		T6	7		T9	11
valid_sources[0x2f]	3502	1			T1	2		T3	15		T6	4
valid_sources[0x30]	4578	1			T1	4		T3	8		T6	9
valid_sources[0x31]	6650	1			T3	10		T6	11		T9	15
valid_sources[0x32]	3345	1			T1	2		T3	17		T6	9
valid_sources[0x33]	3474	1			T1	1		T3	14		T6	12
valid_sources[0x34]	4380	1			T3	12		T5	4		T6	5
valid_sources[0x35]	4035	1			T1	1		T3	10		T5	73
valid_sources[0x36]	3593	1			T1	1		T3	15		T6	3
valid_sources[0x37]	6022	1			T1	1		T3	18		T5	38
valid_sources[0x38]	4039	1			T1	1		T3	10		T5	38
valid_sources[0x39]	4754	1			T1	1		T3	5		T6	16
valid_sources[0x3a]	3934	1			T1	2		T3	13		T5	1
valid_sources[0x3b]	3509	1			T1	3		T3	13		T6	8
valid_sources[0x3c]	3440	1			T1	1		T3	5		T6	4
valid_sources[0x3d]	3881	1			T1	1		T3	5		T5	5
valid_sources[0x3e]	3534	1			T3	21		T6	8		T8	1
valid_sources[0x3f]	6765	1			T1	2		T3	19		T6	9
valid_sources[0x40]	3366	1			T1	2		T3	9		T6	11
valid_sources[0x41]	4232	1			T1	2		T3	11		T5	24
valid_sources[0x42]	5231	1			T3	14		T5	1		T6	7
valid_sources[0x43]	3391	1			T3	12		T6	9		T9	21
valid_sources[0x44]	3427	1			T3	16		T5	29		T6	6
valid_sources[0x45]	6402	1			T3	10		T5	33		T6	18
valid_sources[0x46]	3938	1			T3	4		T5	25		T6	9
valid_sources[0x47]	4193	1			T3	14		T5	8		T6	11
valid_sources[0x48]	4947	1			T1	1		T3	18		T5	29
valid_sources[0x49]	3134	1			T3	11		T6	20		T8	2
valid_sources[0x4a]	4222	1			T1	1		T3	21		T6	14
valid_sources[0x4b]	4370	1			T1	5		T3	8		T6	10
valid_sources[0x4c]	4937	1			T1	1		T3	7		T6	7
valid_sources[0x4d]	3767	1			T1	2		T3	17		T5	1
valid_sources[0x4e]	4592	1			T1	1		T3	9		T5	8
valid_sources[0x4f]	3163	1			T1	1		T3	5		T5	30
valid_sources[0x50]	7284	1			T1	4		T3	15		T6	7
valid_sources[0x51]	4136	1			T3	10		T5	120		T6	4
valid_sources[0x52]	3678	1			T1	4		T3	17		T5	10
valid_sources[0x53]	4394	1			T1	2		T3	12		T5	29
valid_sources[0x54]	4204	1			T1	1		T3	4		T6	14
valid_sources[0x55]	3810	1			T3	9		T6	4		T9	15
valid_sources[0x56]	3927	1			T1	2		T3	13		T6	11
valid_sources[0x57]	4018	1			T1	3		T3	11		T5	12
valid_sources[0x58]	4427	1			T1	2		T3	14		T5	18
valid_sources[0x59]	4401	1			T1	1		T3	16		T5	17
valid_sources[0x5a]	4103	1			T1	1		T3	13		T6	16
valid_sources[0x5b]	3912	1			T1	4		T3	6		T6	12
valid_sources[0x5c]	4946	1			T3	16		T5	15		T6	8
valid_sources[0x5d]	3056	1			T1	1		T3	14		T5	31
valid_sources[0x5e]	3703	1			T1	1		T3	3		T5	38
valid_sources[0x5f]	4251	1			T3	15		T6	8		T9	15
valid_sources[0x60]	3804	1			T3	11		T6	11		T8	4
valid_sources[0x61]	3904	1			T1	2		T3	13		T6	9
valid_sources[0x62]	3568	1			T1	2		T3	10		T6	10
valid_sources[0x63]	3442	1			T1	3		T3	11		T6	7
valid_sources[0x64]	3398	1			T1	1		T3	8		T6	7
valid_sources[0x65]	3853	1			T1	1		T3	16		T6	9
valid_sources[0x66]	3165	1			T1	2		T3	11		T5	8
valid_sources[0x67]	3602	1			T1	3		T3	9		T5	5
valid_sources[0x68]	3038	1			T3	10		T6	12		T8	3
valid_sources[0x69]	3766	1			T3	13		T5	1		T6	2
valid_sources[0x6a]	3160	1			T3	10		T6	13		T8	1
valid_sources[0x6b]	3232	1			T1	1		T3	9		T6	14
valid_sources[0x6c]	4093	1			T1	3		T3	12		T5	7
valid_sources[0x6d]	4129	1			T3	13		T5	65		T6	10
valid_sources[0x6e]	3779	1			T1	1		T3	5		T5	79
valid_sources[0x6f]	3845	1			T1	1		T3	16		T6	12
valid_sources[0x70]	3433	1			T1	8		T3	3		T6	10
valid_sources[0x71]	3899	1			T1	2		T3	17		T6	9
valid_sources[0x72]	6614	1			T1	1		T3	11		T6	5
valid_sources[0x73]	3605	1			T1	2		T3	10		T5	25
valid_sources[0x74]	3112	1			T1	7		T3	8		T6	8
valid_sources[0x75]	3428	1			T3	6		T6	6		T9	17
valid_sources[0x76]	3270	1			T3	12		T6	6		T9	11
valid_sources[0x77]	3495	1			T1	3		T3	14		T5	84
valid_sources[0x78]	5456	1			T1	2		T3	19		T6	7
valid_sources[0x79]	3979	1			T1	2		T3	12		T5	8
valid_sources[0x7a]	3606	1			T3	12		T6	8		T8	1
valid_sources[0x7b]	7918	1			T1	2		T3	11		T5	25
valid_sources[0x7c]	7528	1			T1	1		T3	13		T6	6
valid_sources[0x7d]	3834	1			T1	3		T3	12		T5	6
valid_sources[0x7e]	3220	1			T3	14		T6	12		T8	5
valid_sources[0x7f]	5345	1			T1	6		T3	11		T6	2
valid_sources[0x80]	3211	1			T1	1		T3	13		T5	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

256121

1

T1

83

T3

744

T5

666

values[0x0]

all_enables

biggest_size

83547

1

T1

44

T3

207

T5

279

values[0x1]

all_enables

biggest_size

44346

1

T1

17

T3

103

T5

157