Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T3,T6,T10
1	0	Covered	T1,T3,T6

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55403328	8843	0	0
CascadeEffAonToRstPorAboveRise_A	55403328	8843	0	0
CascadeEffAonToRstPorIoAboveFall_A	53185549	8843	0	0
CascadeEffAonToRstPorIoAboveRise_A	53185549	8843	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26593666	8843	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26593666	8843	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13296521	8843	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13296521	8843	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26593630	8843	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26593630	8843	0	0
CascadeLcToLcAboveFall_A	55403328	22566	0	0
CascadeLcToLcAboveRise_A	55403328	22566	0	0
CascadeLcToLcAonAboveFall_A	1679225	22566	0	0
CascadeLcToLcAonAboveRise_A	1679225	22566	0	0
CascadeLcToLcShadowedAboveFall_A	55403328	22566	0	0
CascadeLcToLcShadowedAboveRise_A	55403328	22566	0	0
CascadePorToAonAboveFall_A	1679225	6950	0	0
CascadeSysToSysAboveFall_A	55403328	22566	0	0
CascadeSysToSysAboveRise_A	55403328	22566	0	0
ScanRstToAonRise_A	1679225	243	0	0
StablePorToAonRise_A	1679225	8843	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11770684	22566	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11770684	22566	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11770684	22566	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11770684	22566	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13296521	22566	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13296521	22566	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11770684	22566	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11770684	22566	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11770684	22566	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11770684	22566	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55403328	8843	0	0
T1	25551	2	0	0
T2	12081	2	0	0
T3	141591	16	0	0
T4	24293	8	0	0
T5	121710	27	0	0
T6	119238	16	0	0
T7	48542	1	0	0
T8	38531	1	0	0
T9	236099	27	0	0
T10	25720	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55403328	8843	0	0
T1	25551	2	0	0
T2	12081	2	0	0
T3	141591	16	0	0
T4	24293	8	0	0
T5	121710	27	0	0
T6	119238	16	0	0
T7	48542	1	0	0
T8	38531	1	0	0
T9	236099	27	0	0
T10	25720	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53185549	8843	0	0
T1	24525	2	0	0
T2	11598	2	0	0
T3	135919	16	0	0
T4	23320	8	0	0
T5	116845	27	0	0
T6	114467	16	0	0
T7	46598	1	0	0
T8	36989	1	0	0
T9	226648	27	0	0
T10	24683	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53185549	8843	0	0
T1	24525	2	0	0
T2	11598	2	0	0
T3	135919	16	0	0
T4	23320	8	0	0
T5	116845	27	0	0
T6	114467	16	0	0
T7	46598	1	0	0
T8	36989	1	0	0
T9	226648	27	0	0
T10	24683	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593666	8843	0	0
T1	12264	2	0	0
T2	5799	2	0	0
T3	67964	16	0	0
T4	11655	8	0	0
T5	58412	27	0	0
T6	57238	16	0	0
T7	23299	1	0	0
T8	18494	1	0	0
T9	113342	27	0	0
T10	12345	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593666	8843	0	0
T1	12264	2	0	0
T2	5799	2	0	0
T3	67964	16	0	0
T4	11655	8	0	0
T5	58412	27	0	0
T6	57238	16	0	0
T7	23299	1	0	0
T8	18494	1	0	0
T9	113342	27	0	0
T10	12345	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	8843	0	0
T1	6130	2	0	0
T2	2899	2	0	0
T3	33981	16	0	0
T4	5826	8	0	0
T5	29212	27	0	0
T6	28617	16	0	0
T7	11649	1	0	0
T8	9245	1	0	0
T9	56664	27	0	0
T10	6170	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	8843	0	0
T1	6130	2	0	0
T2	2899	2	0	0
T3	33981	16	0	0
T4	5826	8	0	0
T5	29212	27	0	0
T6	28617	16	0	0
T7	11649	1	0	0
T8	9245	1	0	0
T9	56664	27	0	0
T10	6170	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593630	8843	0	0
T1	12262	2	0	0
T2	5799	2	0	0
T3	67959	16	0	0
T4	11655	8	0	0
T5	58421	27	0	0
T6	57228	16	0	0
T7	23300	1	0	0
T8	18494	1	0	0
T9	113328	27	0	0
T10	12345	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593630	8843	0	0
T1	12262	2	0	0
T2	5799	2	0	0
T3	67959	16	0	0
T4	11655	8	0	0
T5	58421	27	0	0
T6	57228	16	0	0
T7	23300	1	0	0
T8	18494	1	0	0
T9	113328	27	0	0
T10	12345	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55403328	22566	0	0
T1	25551	6	0	0
T2	12081	2	0	0
T3	141591	57	0	0
T4	24293	8	0	0
T5	121710	102	0	0
T6	119238	44	0	0
T7	48542	1	0	0
T8	38531	1	0	0
T9	236099	102	0	0
T10	25720	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55403328	22566	0	0
T1	25551	6	0	0
T2	12081	2	0	0
T3	141591	57	0	0
T4	24293	8	0	0
T5	121710	102	0	0
T6	119238	44	0	0
T7	48542	1	0	0
T8	38531	1	0	0
T9	236099	102	0	0
T10	25720	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679225	22566	0	0
T1	766	6	0	0
T2	360	2	0	0
T3	4342	57	0	0
T4	730	8	0	0
T5	3666	102	0	0
T6	3660	44	0	0
T7	1454	1	0	0
T8	1155	1	0	0
T9	7099	102	0	0
T10	771	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679225	22566	0	0
T1	766	6	0	0
T2	360	2	0	0
T3	4342	57	0	0
T4	730	8	0	0
T5	3666	102	0	0
T6	3660	44	0	0
T7	1454	1	0	0
T8	1155	1	0	0
T9	7099	102	0	0
T10	771	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55403328	22566	0	0
T1	25551	6	0	0
T2	12081	2	0	0
T3	141591	57	0	0
T4	24293	8	0	0
T5	121710	102	0	0
T6	119238	44	0	0
T7	48542	1	0	0
T8	38531	1	0	0
T9	236099	102	0	0
T10	25720	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55403328	22566	0	0
T1	25551	6	0	0
T2	12081	2	0	0
T3	141591	57	0	0
T4	24293	8	0	0
T5	121710	102	0	0
T6	119238	44	0	0
T7	48542	1	0	0
T8	38531	1	0	0
T9	236099	102	0	0
T10	25720	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679225	6950	0	0
T1	766	1	0	0
T2	360	9	0	0
T3	4342	9	0	0
T4	730	8	0	0
T5	3666	27	0	0
T6	3660	10	0	0
T7	1454	1	0	0
T8	1155	1	0	0
T9	7099	27	0	0
T10	771	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55403328	22566	0	0
T1	25551	6	0	0
T2	12081	2	0	0
T3	141591	57	0	0
T4	24293	8	0	0
T5	121710	102	0	0
T6	119238	44	0	0
T7	48542	1	0	0
T8	38531	1	0	0
T9	236099	102	0	0
T10	25720	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55403328	22566	0	0
T1	25551	6	0	0
T2	12081	2	0	0
T3	141591	57	0	0
T4	24293	8	0	0
T5	121710	102	0	0
T6	119238	44	0	0
T7	48542	1	0	0
T8	38531	1	0	0
T9	236099	102	0	0
T10	25720	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679225	243	0	0
T6	3660	1	0	0
T7	1454	0	0	0
T8	1155	0	0	0
T9	7099	0	0	0
T10	771	0	0	0
T11	519	0	0	0
T12	24140	5	0	0
T13	300	0	0	0
T36	0	1	0	0
T41	0	5	0	0
T47	401	0	0	0
T48	173	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T97	0	2	0	0
T99	0	5	0	0
T133	0	1	0	0
T134	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679225	8843	0	0
T1	766	2	0	0
T2	360	2	0	0
T3	4342	16	0	0
T4	730	8	0	0
T5	3666	27	0	0
T6	3660	16	0	0
T7	1454	1	0	0
T8	1155	1	0	0
T9	7099	27	0	0
T10	771	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11770684	22566	0	0
T1	5936	6	0	0
T2	2808	2	0	0
T3	29451	57	0	0
T4	5475	8	0	0
T5	26142	102	0	0
T6	25113	44	0	0
T7	11630	1	0	0
T8	9204	1	0	0
T9	53633	102	0	0
T10	5833	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11770684	22566	0	0
T1	5936	6	0	0
T2	2808	2	0	0
T3	29451	57	0	0
T4	5475	8	0	0
T5	26142	102	0	0
T6	25113	44	0	0
T7	11630	1	0	0
T8	9204	1	0	0
T9	53633	102	0	0
T10	5833	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11770684	22566	0	0
T1	5936	6	0	0
T2	2808	2	0	0
T3	29451	57	0	0
T4	5475	8	0	0
T5	26142	102	0	0
T6	25113	44	0	0
T7	11630	1	0	0
T8	9204	1	0	0
T9	53633	102	0	0
T10	5833	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11770684	22566	0	0
T1	5936	6	0	0
T2	2808	2	0	0
T3	29451	57	0	0
T4	5475	8	0	0
T5	26142	102	0	0
T6	25113	44	0	0
T7	11630	1	0	0
T8	9204	1	0	0
T9	53633	102	0	0
T10	5833	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	22566	0	0
T1	6130	6	0	0
T2	2899	2	0	0
T3	33981	57	0	0
T4	5826	8	0	0
T5	29212	102	0	0
T6	28617	44	0	0
T7	11649	1	0	0
T8	9245	1	0	0
T9	56664	102	0	0
T10	6170	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	22566	0	0
T1	6130	6	0	0
T2	2899	2	0	0
T3	33981	57	0	0
T4	5826	8	0	0
T5	29212	102	0	0
T6	28617	44	0	0
T7	11649	1	0	0
T8	9245	1	0	0
T9	56664	102	0	0
T10	6170	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11770684	22566	0	0
T1	5936	6	0	0
T2	2808	2	0	0
T3	29451	57	0	0
T4	5475	8	0	0
T5	26142	102	0	0
T6	25113	44	0	0
T7	11630	1	0	0
T8	9204	1	0	0
T9	53633	102	0	0
T10	5833	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11770684	22566	0	0
T1	5936	6	0	0
T2	2808	2	0	0
T3	29451	57	0	0
T4	5475	8	0	0
T5	26142	102	0	0
T6	25113	44	0	0
T7	11630	1	0	0
T8	9204	1	0	0
T9	53633	102	0	0
T10	5833	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11770684	22566	0	0
T1	5936	6	0	0
T2	2808	2	0	0
T3	29451	57	0	0
T4	5475	8	0	0
T5	26142	102	0	0
T6	25113	44	0	0
T7	11630	1	0	0
T8	9204	1	0	0
T9	53633	102	0	0
T10	5833	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11770684	22566	0	0
T1	5936	6	0	0
T2	2808	2	0	0
T3	29451	57	0	0
T4	5475	8	0	0
T5	26142	102	0	0
T6	25113	44	0	0
T7	11630	1	0	0
T8	9204	1	0	0
T9	53633	102	0	0
T10	5833	6	0	0