Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T47
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T47
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T47
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T47
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T47
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T47
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13296521	14627	0	0
gen_assertions[0].RstEnOn_A	13296521	1080	0	0
gen_assertions[0].RstNOff_A	13296521	14627	0	0
gen_assertions[0].RstNOn_A	13296521	1080	0	0
gen_assertions[1].RstEnOff_A	53185549	13294	0	0
gen_assertions[1].RstEnOn_A	53185549	1019	0	0
gen_assertions[1].RstNOff_A	53185549	13294	0	0
gen_assertions[1].RstNOn_A	53185549	1019	0	0
gen_assertions[2].RstEnOff_A	26593666	13336	0	0
gen_assertions[2].RstEnOn_A	26593666	1009	0	0
gen_assertions[2].RstNOff_A	26593666	13336	0	0
gen_assertions[2].RstNOn_A	26593666	1009	0	0
gen_assertions[3].RstEnOff_A	26593630	13394	0	0
gen_assertions[3].RstEnOn_A	26593630	1060	0	0
gen_assertions[3].RstNOff_A	26593630	13394	0	0
gen_assertions[3].RstNOn_A	26593630	1060	0	0
gen_assertions[4].RstEnOff_A	1679225	22345	0	0
gen_assertions[4].RstEnOn_A	1679225	1092	0	0
gen_assertions[4].RstNOff_A	1679225	22345	0	0
gen_assertions[4].RstNOn_A	1679225	1092	0	0
gen_assertions[5].RstEnOff_A	13296521	14817	0	0
gen_assertions[5].RstEnOn_A	13296521	1131	0	0
gen_assertions[5].RstNOff_A	13296521	14817	0	0
gen_assertions[5].RstNOn_A	13296521	1131	0	0
gen_assertions[6].RstEnOff_A	13296521	14904	0	0
gen_assertions[6].RstEnOn_A	13296521	1212	0	0
gen_assertions[6].RstNOff_A	13296521	14904	0	0
gen_assertions[6].RstNOn_A	13296521	1212	0	0
gen_assertions[7].RstEnOff_A	13296521	14958	0	0
gen_assertions[7].RstEnOn_A	13296521	1271	0	0
gen_assertions[7].RstNOff_A	13296521	14958	0	0
gen_assertions[7].RstNOn_A	13296521	1271	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	14627	0	0
T1	6130	5	0	0
T2	2899	0	0	0
T3	33981	41	0	0
T4	5826	0	0	0
T5	29212	75	0	0
T6	28617	28	0	0
T7	11649	6	0	0
T8	9245	2	0	0
T9	56664	75	0	0
T10	6170	4	0	0
T11	0	4	0	0
T47	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	1080	0	0
T1	6130	1	0	0
T2	2899	0	0	0
T3	33981	0	0	0
T4	5826	0	0	0
T5	29212	0	0	0
T6	28617	0	0	0
T7	11649	6	0	0
T8	9245	2	0	0
T9	56664	0	0	0
T10	6170	0	0	0
T12	0	17	0	0
T22	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T41	0	21	0	0
T47	0	5	0	0
T80	0	5	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	14627	0	0
T1	6130	5	0	0
T2	2899	0	0	0
T3	33981	41	0	0
T4	5826	0	0	0
T5	29212	75	0	0
T6	28617	28	0	0
T7	11649	6	0	0
T8	9245	2	0	0
T9	56664	75	0	0
T10	6170	4	0	0
T11	0	4	0	0
T47	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	1080	0	0
T1	6130	1	0	0
T2	2899	0	0	0
T3	33981	0	0	0
T4	5826	0	0	0
T5	29212	0	0	0
T6	28617	0	0	0
T7	11649	6	0	0
T8	9245	2	0	0
T9	56664	0	0	0
T10	6170	0	0	0
T12	0	17	0	0
T22	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T41	0	21	0	0
T47	0	5	0	0
T80	0	5	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53185549	13294	0	0
T1	24525	4	0	0
T2	11598	0	0	0
T3	135919	38	0	0
T4	23320	0	0	0
T5	116845	71	0	0
T6	114467	26	0	0
T7	46598	4	0	0
T8	36989	2	0	0
T9	226648	64	0	0
T10	24683	4	0	0
T11	0	4	0	0
T47	0	5	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53185549	1019	0	0
T7	46598	4	0	0
T8	36989	2	0	0
T9	226648	0	0	0
T10	24683	0	0	0
T11	16671	0	0	0
T12	765955	15	0	0
T13	9618	0	0	0
T24	23355	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	16	0	0
T47	12869	5	0	0
T48	5565	0	0	0
T80	0	7	0	0
T81	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53185549	13294	0	0
T1	24525	4	0	0
T2	11598	0	0	0
T3	135919	38	0	0
T4	23320	0	0	0
T5	116845	71	0	0
T6	114467	26	0	0
T7	46598	4	0	0
T8	36989	2	0	0
T9	226648	64	0	0
T10	24683	4	0	0
T11	0	4	0	0
T47	0	5	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53185549	1019	0	0
T7	46598	4	0	0
T8	36989	2	0	0
T9	226648	0	0	0
T10	24683	0	0	0
T11	16671	0	0	0
T12	765955	15	0	0
T13	9618	0	0	0
T24	23355	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	16	0	0
T47	12869	5	0	0
T48	5565	0	0	0
T80	0	7	0	0
T81	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593666	13336	0	0
T1	12264	4	0	0
T2	5799	0	0	0
T3	67964	38	0	0
T4	11655	0	0	0
T5	58412	71	0	0
T6	57238	26	0	0
T7	23299	8	0	0
T8	18494	2	0	0
T9	113342	64	0	0
T10	12345	4	0	0
T11	0	4	0	0
T47	0	7	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593666	1009	0	0
T7	23299	8	0	0
T8	18494	2	0	0
T9	113342	0	0	0
T10	12345	0	0	0
T11	8334	0	0	0
T12	383008	19	0	0
T13	4808	0	0	0
T24	11683	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	22	0	0
T47	6434	7	0	0
T48	2782	0	0	0
T80	0	7	0	0
T82	0	1	0	0
T83	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593666	13336	0	0
T1	12264	4	0	0
T2	5799	0	0	0
T3	67964	38	0	0
T4	11655	0	0	0
T5	58412	71	0	0
T6	57238	26	0	0
T7	23299	8	0	0
T8	18494	2	0	0
T9	113342	64	0	0
T10	12345	4	0	0
T11	0	4	0	0
T47	0	7	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593666	1009	0	0
T7	23299	8	0	0
T8	18494	2	0	0
T9	113342	0	0	0
T10	12345	0	0	0
T11	8334	0	0	0
T12	383008	19	0	0
T13	4808	0	0	0
T24	11683	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	22	0	0
T47	6434	7	0	0
T48	2782	0	0	0
T80	0	7	0	0
T82	0	1	0	0
T83	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593630	13394	0	0
T1	12262	4	0	0
T2	5799	0	0	0
T3	67959	38	0	0
T4	11655	0	0	0
T5	58421	71	0	0
T6	57228	26	0	0
T7	23300	8	0	0
T8	18494	5	0	0
T9	113328	64	0	0
T10	12345	4	0	0
T11	0	4	0	0
T47	0	9	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593630	1060	0	0
T7	23300	8	0	0
T8	18494	5	0	0
T9	113328	0	0	0
T10	12345	0	0	0
T11	8334	0	0	0
T12	382995	20	0	0
T13	4808	0	0	0
T24	11674	0	0	0
T35	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T41	0	18	0	0
T47	6433	9	0	0
T48	2782	0	0	0
T80	0	8	0	0
T84	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593630	13394	0	0
T1	12262	4	0	0
T2	5799	0	0	0
T3	67959	38	0	0
T4	11655	0	0	0
T5	58421	71	0	0
T6	57228	26	0	0
T7	23300	8	0	0
T8	18494	5	0	0
T9	113328	64	0	0
T10	12345	4	0	0
T11	0	4	0	0
T47	0	9	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26593630	1060	0	0
T7	23300	8	0	0
T8	18494	5	0	0
T9	113328	0	0	0
T10	12345	0	0	0
T11	8334	0	0	0
T12	382995	20	0	0
T13	4808	0	0	0
T24	11674	0	0	0
T35	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T41	0	18	0	0
T47	6433	9	0	0
T48	2782	0	0	0
T80	0	8	0	0
T84	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679225	22345	0	0
T1	766	6	0	0
T2	360	2	0	0
T3	4342	56	0	0
T4	730	3	0	0
T5	3666	77	0	0
T6	3660	44	0	0
T7	1454	12	0	0
T8	1155	7	0	0
T9	7099	95	0	0
T10	771	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679225	1092	0	0
T7	1454	11	0	0
T8	1155	6	0	0
T9	7099	0	0	0
T10	771	0	0	0
T11	519	0	0	0
T12	24140	17	0	0
T13	300	0	0	0
T24	732	0	0	0
T37	0	5	0	0
T38	0	5	0	0
T41	0	16	0	0
T47	401	9	0	0
T48	173	0	0	0
T80	0	7	0	0
T84	0	6	0	0
T85	0	6	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679225	22345	0	0
T1	766	6	0	0
T2	360	2	0	0
T3	4342	56	0	0
T4	730	3	0	0
T5	3666	77	0	0
T6	3660	44	0	0
T7	1454	12	0	0
T8	1155	7	0	0
T9	7099	95	0	0
T10	771	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679225	1092	0	0
T7	1454	11	0	0
T8	1155	6	0	0
T9	7099	0	0	0
T10	771	0	0	0
T11	519	0	0	0
T12	24140	17	0	0
T13	300	0	0	0
T24	732	0	0	0
T37	0	5	0	0
T38	0	5	0	0
T41	0	16	0	0
T47	401	9	0	0
T48	173	0	0	0
T80	0	7	0	0
T84	0	6	0	0
T85	0	6	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	14817	0	0
T1	6130	5	0	0
T2	2899	0	0	0
T3	33981	41	0	0
T4	5826	0	0	0
T5	29212	75	0	0
T6	28617	28	0	0
T7	11649	11	0	0
T8	9245	7	0	0
T9	56664	75	0	0
T10	6170	4	0	0
T11	0	4	0	0
T47	0	12	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	1131	0	0
T1	6130	1	0	0
T2	2899	0	0	0
T3	33981	0	0	0
T4	5826	0	0	0
T5	29212	0	0	0
T6	28617	0	0	0
T7	11649	11	0	0
T8	9245	7	0	0
T9	56664	0	0	0
T10	6170	0	0	0
T12	0	16	0	0
T37	0	5	0	0
T38	0	5	0	0
T41	0	19	0	0
T47	0	12	0	0
T80	0	7	0	0
T84	0	5	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	14817	0	0
T1	6130	5	0	0
T2	2899	0	0	0
T3	33981	41	0	0
T4	5826	0	0	0
T5	29212	75	0	0
T6	28617	28	0	0
T7	11649	11	0	0
T8	9245	7	0	0
T9	56664	75	0	0
T10	6170	4	0	0
T11	0	4	0	0
T47	0	12	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	1131	0	0
T1	6130	1	0	0
T2	2899	0	0	0
T3	33981	0	0	0
T4	5826	0	0	0
T5	29212	0	0	0
T6	28617	0	0	0
T7	11649	11	0	0
T8	9245	7	0	0
T9	56664	0	0	0
T10	6170	0	0	0
T12	0	16	0	0
T37	0	5	0	0
T38	0	5	0	0
T41	0	19	0	0
T47	0	12	0	0
T80	0	7	0	0
T84	0	5	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	14904	0	0
T1	6130	4	0	0
T2	2899	0	0	0
T3	33981	41	0	0
T4	5826	0	0	0
T5	29212	75	0	0
T6	28617	28	0	0
T7	11649	14	0	0
T8	9245	8	0	0
T9	56664	75	0	0
T10	6170	4	0	0
T11	0	4	0	0
T47	0	12	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	1212	0	0
T7	11649	14	0	0
T8	9245	8	0	0
T9	56664	0	0	0
T10	6170	0	0	0
T11	4166	0	0	0
T12	191495	22	0	0
T13	2403	0	0	0
T24	5834	0	0	0
T37	0	8	0	0
T38	0	7	0	0
T41	0	17	0	0
T47	3216	12	0	0
T48	1390	0	0	0
T80	0	5	0	0
T84	0	8	0	0
T85	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	14904	0	0
T1	6130	4	0	0
T2	2899	0	0	0
T3	33981	41	0	0
T4	5826	0	0	0
T5	29212	75	0	0
T6	28617	28	0	0
T7	11649	14	0	0
T8	9245	8	0	0
T9	56664	75	0	0
T10	6170	4	0	0
T11	0	4	0	0
T47	0	12	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	1212	0	0
T7	11649	14	0	0
T8	9245	8	0	0
T9	56664	0	0	0
T10	6170	0	0	0
T11	4166	0	0	0
T12	191495	22	0	0
T13	2403	0	0	0
T24	5834	0	0	0
T37	0	8	0	0
T38	0	7	0	0
T41	0	17	0	0
T47	3216	12	0	0
T48	1390	0	0	0
T80	0	5	0	0
T84	0	8	0	0
T85	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	14958	0	0
T1	6130	4	0	0
T2	2899	0	0	0
T3	33981	41	0	0
T4	5826	0	0	0
T5	29212	75	0	0
T6	28617	28	0	0
T7	11649	13	0	0
T8	9245	9	0	0
T9	56664	75	0	0
T10	6170	4	0	0
T11	0	4	0	0
T47	0	11	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	1271	0	0
T7	11649	13	0	0
T8	9245	9	0	0
T9	56664	0	0	0
T10	6170	0	0	0
T11	4166	0	0	0
T12	191495	15	0	0
T13	2403	0	0	0
T24	5834	0	0	0
T37	0	9	0	0
T38	0	8	0	0
T41	0	16	0	0
T47	3216	11	0	0
T48	1390	0	0	0
T80	0	7	0	0
T84	0	10	0	0
T85	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	14958	0	0
T1	6130	4	0	0
T2	2899	0	0	0
T3	33981	41	0	0
T4	5826	0	0	0
T5	29212	75	0	0
T6	28617	28	0	0
T7	11649	13	0	0
T8	9245	9	0	0
T9	56664	75	0	0
T10	6170	4	0	0
T11	0	4	0	0
T47	0	11	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13296521	1271	0	0
T7	11649	13	0	0
T8	9245	9	0	0
T9	56664	0	0	0
T10	6170	0	0	0
T11	4166	0	0	0
T12	191495	15	0	0
T13	2403	0	0	0
T24	5834	0	0	0
T37	0	9	0	0
T38	0	8	0	0
T41	0	16	0	0
T47	3216	11	0	0
T48	1390	0	0	0
T80	0	7	0	0
T84	0	10	0	0
T85	0	8	0	0