Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12556743	8924	0	0
alert_regwen_rd_A	12556743	4357	0	0
cpu_regwen_rd_A	12556743	4391	0	0
sw_rst_ctrl_n_0_rd_A	12556743	10514	0	0
sw_rst_ctrl_n_1_rd_A	12556743	10058	0	0
sw_rst_ctrl_n_2_rd_A	12556743	10539	0	0
sw_rst_ctrl_n_3_rd_A	12556743	10461	0	0
sw_rst_ctrl_n_4_rd_A	12556743	10166	0	0
sw_rst_ctrl_n_5_rd_A	12556743	10028	0	0
sw_rst_ctrl_n_6_rd_A	12556743	10488	0	0
sw_rst_ctrl_n_7_rd_A	12556743	10157	0	0
sw_rst_regwen_0_rd_A	12556743	5179	0	0
sw_rst_regwen_1_rd_A	12556743	4983	0	0
sw_rst_regwen_2_rd_A	12556743	5087	0	0
sw_rst_regwen_3_rd_A	12556743	5123	0	0
sw_rst_regwen_4_rd_A	12556743	5003	0	0
sw_rst_regwen_5_rd_A	12556743	5040	0	0
sw_rst_regwen_6_rd_A	12556743	5122	0	0
sw_rst_regwen_7_rd_A	12556743	5161	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	8924	0	0
T58	4554	41	0	0
T61	4341	143	0	0
T62	16983	2	0	0
T63	3818	6	0	0
T87	4624	25	0	0
T88	2588	171	0	0
T89	11980	629	0	0
T90	4391	549	0	0
T93	17530	4	0	0
T112	9033	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	4357	0	0
T12	171523	106	0	0
T13	2337	0	0	0
T22	4639	0	0	0
T23	48902	0	0	0
T24	5101	0	0	0
T34	5081	0	0	0
T35	6043	0	0	0
T41	0	279	0	0
T48	1324	0	0	0
T52	2078	0	0	0
T79	5676	0	0	0
T95	0	52	0	0
T101	0	72	0	0
T102	0	68	0	0
T126	0	64	0	0
T127	0	138	0	0
T128	0	348	0	0
T129	0	80	0	0
T130	0	225	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	4391	0	0
T12	171523	115	0	0
T13	2337	0	0	0
T22	4639	0	0	0
T23	48902	0	0	0
T24	5101	0	0	0
T34	5081	0	0	0
T35	6043	0	0	0
T41	0	328	0	0
T48	1324	0	0	0
T52	2078	0	0	0
T79	5676	0	0	0
T95	0	38	0	0
T101	0	108	0	0
T102	0	66	0	0
T126	0	92	0	0
T127	0	97	0	0
T128	0	367	0	0
T129	0	84	0	0
T130	0	188	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	10514	0	0
T1	5936	13	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	203	0	0
T8	9204	129	0	0
T9	53633	0	0	0
T10	5833	22	0	0
T12	0	316	0	0
T22	0	59	0	0
T35	0	22	0	0
T41	0	496	0	0
T82	0	13	0	0
T95	0	26	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	10058	0	0
T1	5936	10	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	190	0	0
T8	9204	111	0	0
T9	53633	0	0	0
T10	5833	9	0	0
T12	0	261	0	0
T22	0	54	0	0
T35	0	7	0	0
T41	0	512	0	0
T82	0	11	0	0
T95	0	59	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	10539	0	0
T1	5936	10	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	175	0	0
T8	9204	111	0	0
T9	53633	0	0	0
T10	5833	10	0	0
T12	0	325	0	0
T22	0	74	0	0
T35	0	13	0	0
T41	0	529	0	0
T82	0	13	0	0
T95	0	61	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	10461	0	0
T1	5936	27	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	177	0	0
T8	9204	99	0	0
T9	53633	0	0	0
T10	5833	8	0	0
T12	0	286	0	0
T22	0	63	0	0
T35	0	13	0	0
T41	0	506	0	0
T82	0	10	0	0
T95	0	20	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	10166	0	0
T1	5936	7	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	186	0	0
T8	9204	126	0	0
T9	53633	0	0	0
T10	5833	14	0	0
T12	0	266	0	0
T22	0	43	0	0
T35	0	25	0	0
T41	0	505	0	0
T82	0	10	0	0
T95	0	32	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	10028	0	0
T1	5936	10	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	188	0	0
T8	9204	118	0	0
T9	53633	0	0	0
T10	5833	16	0	0
T12	0	246	0	0
T22	0	56	0	0
T35	0	11	0	0
T41	0	503	0	0
T82	0	9	0	0
T95	0	57	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	10488	0	0
T1	5936	11	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	147	0	0
T8	9204	136	0	0
T9	53633	0	0	0
T10	5833	16	0	0
T12	0	287	0	0
T22	0	58	0	0
T35	0	14	0	0
T41	0	588	0	0
T82	0	12	0	0
T95	0	50	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	10157	0	0
T1	5936	20	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	191	0	0
T8	9204	111	0	0
T9	53633	0	0	0
T10	5833	27	0	0
T12	0	251	0	0
T22	0	39	0	0
T35	0	15	0	0
T41	0	556	0	0
T82	0	14	0	0
T95	0	55	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	5179	0	0
T1	5936	9	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	37	0	0
T8	9204	12	0	0
T9	53633	0	0	0
T10	5833	10	0	0
T12	0	127	0	0
T35	0	8	0	0
T41	0	313	0	0
T82	0	9	0	0
T95	0	48	0	0
T131	0	10	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	4983	0	0
T1	5936	8	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	28	0	0
T8	9204	28	0	0
T9	53633	0	0	0
T10	5833	5	0	0
T12	0	131	0	0
T35	0	11	0	0
T41	0	328	0	0
T82	0	6	0	0
T95	0	52	0	0
T131	0	7	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	5087	0	0
T1	5936	8	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	35	0	0
T8	9204	39	0	0
T9	53633	0	0	0
T10	5833	13	0	0
T12	0	144	0	0
T35	0	12	0	0
T41	0	276	0	0
T82	0	4	0	0
T95	0	65	0	0
T131	0	4	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	5123	0	0
T1	5936	11	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	27	0	0
T8	9204	33	0	0
T9	53633	0	0	0
T10	5833	4	0	0
T12	0	133	0	0
T35	0	8	0	0
T41	0	291	0	0
T82	0	10	0	0
T95	0	32	0	0
T131	0	3	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	5003	0	0
T1	5936	2	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	28	0	0
T8	9204	32	0	0
T9	53633	0	0	0
T10	5833	0	0	0
T12	0	117	0	0
T41	0	266	0	0
T75	0	37	0	0
T82	0	15	0	0
T95	0	47	0	0
T131	0	7	0	0
T132	0	43	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	5040	0	0
T1	5936	10	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	39	0	0
T8	9204	27	0	0
T9	53633	0	0	0
T10	5833	5	0	0
T12	0	142	0	0
T35	0	4	0	0
T41	0	264	0	0
T82	0	3	0	0
T95	0	55	0	0
T131	0	7	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	5122	0	0
T1	5936	8	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	25	0	0
T8	9204	21	0	0
T9	53633	0	0	0
T10	5833	2	0	0
T12	0	109	0	0
T35	0	14	0	0
T41	0	271	0	0
T95	0	36	0	0
T131	0	4	0	0
T132	0	23	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12556743	5161	0	0
T1	5936	12	0	0
T2	2808	0	0	0
T3	29451	0	0	0
T4	5475	0	0	0
T5	26142	0	0	0
T6	25113	0	0	0
T7	11630	28	0	0
T8	9204	21	0	0
T9	53633	0	0	0
T10	5833	8	0	0
T12	0	111	0	0
T35	0	15	0	0
T41	0	235	0	0
T82	0	7	0	0
T95	0	55	0	0
T131	0	13	0	0