Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg

Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sw_rst_ctrl_n[0]	100.00	1	100	1	64	64
sw_rst_ctrl_n[1]	100.00	1	100	1	64	64
sw_rst_ctrl_n[2]	100.00	1	100	1	64	64
sw_rst_ctrl_n[3]	100.00	1	100	1	64	64
sw_rst_ctrl_n[4]	100.00	1	100	1	64	64
sw_rst_ctrl_n[5]	100.00	1	100	1	64	64
sw_rst_ctrl_n[6]	100.00	1	100	1	64	64
sw_rst_ctrl_n[7]	100.00	1	100	1	64	64

---

Group Instance : sw_rst_ctrl_n[0]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[0]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[0]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[0]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[1]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[1]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[1]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[1]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[2]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[2]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[2]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[2]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[3]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[3]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[3]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[3]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[4]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[4]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[4]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[4]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[5]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[5]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[5]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[5]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[6]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[6]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[6]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[6]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[7]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[7]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[7]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[7]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T4

32

T25

32

T31

32

auto[1]

4607

1

T3

22

T4

19

T5

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T4

32

T25

32

T31

32

auto[1]

4607

1

T3

22

T4

19

T5

3

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1823

1

T3

4

T4

14

T10

12

auto[1]

4384

1

T3

18

T4

37

T5

3

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1823

1

T3

4

T4

14

T10

12

auto[1]

4384

1

T3

18

T4

37

T5

3

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

400

1

T4

8

T25

8

T31

8

auto[0]

auto[1]

1200

1

T4

24

T25

24

T31

24

auto[1]

auto[0]

1423

1

T3

4

T4

6

T10

12

auto[1]

auto[1]

3184

1

T3

18

T4

13

T5

3

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1487

1

T4

28

T5

3

T6

3

auto[1]

4496

1

T3

14

T4

23

T10

31

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1487

1

T4

28

T5

3

T6

3

auto[1]

4496

1

T3

14

T4

23

T10

31

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1696

1

T4

10

T5

1

T6

2

auto[1]

4287

1

T3

14

T4

41

T5

2

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1696

1

T4

10

T5

1

T6

2

auto[1]

4287

1

T3

14

T4

41

T5

2

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

401

1

T4

7

T5

1

T6

2

auto[0]

auto[1]

1086

1

T4

21

T5

2

T6

1

auto[1]

auto[0]

1295

1

T4

3

T10

13

T25

12

auto[1]

auto[1]

3201

1

T3

14

T4

20

T10

18

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1272

1

T4

24

T5

3

T11

3

auto[1]

4625

1

T3

14

T4

27

T6

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1272

1

T4

24

T5

3

T11

3

auto[1]

4625

1

T3

14

T4

27

T6

3

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1706

1

T4

13

T5

2

T10

13

auto[1]

4191

1

T3

14

T4

38

T5

1

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1706

1

T4

13

T5

2

T10

13

auto[1]

4191

1

T3

14

T4

38

T5

1

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

337

1

T4

6

T5

2

T11

1

auto[0]

auto[1]

935

1

T4

18

T5

1

T11

2

auto[1]

auto[0]

1369

1

T4

7

T10

13

T25

11

auto[1]

auto[1]

3256

1

T3

14

T4

20

T6

3

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T4

20

T11

3

T25

20

auto[1]

4821

1

T3

14

T4

31

T5

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T4

20

T11

3

T25

20

auto[1]

4821

1

T3

14

T4

31

T5

3

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1624

1

T4

14

T6

1

T10

10

auto[1]

4260

1

T3

14

T4

37

T5

3

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1624

1

T4

14

T6

1

T10

10

auto[1]

4260

1

T3

14

T4

37

T5

3

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

279

1

T4

5

T11

2

T25

5

auto[0]

auto[1]

784

1

T4

15

T11

1

T25

15

auto[1]

auto[0]

1345

1

T4

9

T6

1

T10

10

auto[1]

auto[1]

3476

1

T3

14

T4

22

T5

3

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

875

1

T4

16

T5

3

T11

3

auto[1]

5009

1

T3

14

T4

35

T6

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

875

1

T4

16

T5

3

T11

3

auto[1]

5009

1

T3

14

T4

35

T6

3

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1695

1

T4

14

T5

1

T10

11

auto[1]

4189

1

T3

14

T4

37

T5

2

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1695

1

T4

14

T5

1

T10

11

auto[1]

4189

1

T3

14

T4

37

T5

2

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

236

1

T4

4

T5

1

T11

2

auto[0]

auto[1]

639

1

T4

12

T5

2

T11

1

auto[1]

auto[0]

1459

1

T4

10

T10

11

T25

14

auto[1]

auto[1]

3550

1

T3

14

T4

25

T6

3

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

681

1

T4

12

T11

3

T25

12

auto[1]

5203

1

T3

14

T4

39

T5

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

681

1

T4

12

T11

3

T25

12

auto[1]

5203

1

T3

14

T4

39

T5

3

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1648

1

T4

13

T6

1

T10

10

auto[1]

4236

1

T3

14

T4

38

T5

3

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1648

1

T4

13

T6

1

T10

10

auto[1]

4236

1

T3

14

T4

38

T5

3

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

188

1

T4

3

T11

2

T25

3

auto[0]

auto[1]

493

1

T4

9

T11

1

T25

9

auto[1]

auto[0]

1460

1

T4

10

T6

1

T10

10

auto[1]

auto[1]

3743

1

T3

14

T4

29

T5

3

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

469

1

T4

8

T5

3

T6

3

auto[1]

5415

1

T3

14

T4

43

T10

31

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

469

1

T4

8

T5

3

T6

3

auto[1]

5415

1

T3

14

T4

43

T10

31

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1691

1

T4

13

T5

1

T6

1

auto[1]

4193

1

T3

14

T4

38

T5

2

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1691

1

T4

13

T5

1

T6

1

auto[1]

4193

1

T3

14

T4

38

T5

2

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

136

1

T4

2

T5

1

T6

1

auto[0]

auto[1]

333

1

T4

6

T5

2

T6

2

auto[1]

auto[0]

1555

1

T4

11

T10

12

T25

15

auto[1]

auto[1]

3860

1

T3

14

T4

32

T10

19

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272

1

T4

4

T25

4

T31

4

auto[1]

5612

1

T3

14

T4

47

T5

3

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272

1

T4

4

T25

4

T31

4

auto[1]

5612

1

T3

14

T4

47

T5

3

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1671

1

T4

17

T10

12

T25

21

auto[1]

4213

1

T3

14

T4

34

T5

3

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1671

1

T4

17

T10

12

T25

21

auto[1]

4213

1

T3

14

T4

34

T5

3

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

87

1

T4

1

T25

1

T31

1

auto[0]

auto[1]

185

1

T4

3

T25

3

T31

3

auto[1]

auto[0]

1584

1

T4

16

T10

12

T25

20

auto[1]

auto[1]

4028

1

T3

14

T4

31

T5

3