Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	634978	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

382674

1

T1

1160

T3

99

T4

359

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	544496	1			T1	1746		T2	20		T3	126
values[0x0]	236427	1			T1	706		T3	72		T4	219
values[0x1]	236729	1			T1	693		T3	61		T4	226

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	532718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

484934

1

T1

1476

T2

2

T3

126

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3561	1			T5	3		T9	11		T10	21
valid_sources[0x01]	4226	1			T1	38		T3	1		T9	14
valid_sources[0x02]	3593	1			T1	23		T2	1		T9	10
valid_sources[0x03]	3377	1			T1	14		T2	1		T4	2
valid_sources[0x04]	4358	1			T1	12		T9	9		T10	25
valid_sources[0x05]	3576	1			T1	6		T3	2		T9	8
valid_sources[0x06]	4034	1			T1	7		T3	2		T9	14
valid_sources[0x07]	3715	1			T1	20		T4	3		T9	6
valid_sources[0x08]	4501	1			T1	17		T2	1		T3	2
valid_sources[0x09]	3867	1			T1	11		T4	4		T9	15
valid_sources[0x0a]	4083	1			T1	8		T9	9		T10	23
valid_sources[0x0b]	4158	1			T1	14		T3	2		T9	16
valid_sources[0x0c]	3755	1			T3	2		T9	8		T10	17
valid_sources[0x0d]	3590	1			T4	12		T5	12		T9	10
valid_sources[0x0e]	4007	1			T1	21		T4	29		T9	9
valid_sources[0x0f]	3851	1			T3	2		T5	6		T9	9
valid_sources[0x10]	7076	1			T4	1		T9	15		T10	30
valid_sources[0x11]	4020	1			T3	3		T5	2		T9	4
valid_sources[0x12]	3753	1			T9	13		T10	25		T11	1
valid_sources[0x13]	3524	1			T4	38		T9	16		T10	38
valid_sources[0x14]	5672	1			T1	12		T3	1		T9	8
valid_sources[0x15]	3456	1			T3	1		T4	1		T9	15
valid_sources[0x16]	4130	1			T1	20		T9	6		T10	34
valid_sources[0x17]	3857	1			T1	4		T3	3		T9	9
valid_sources[0x18]	3323	1			T1	27		T9	19		T10	49
valid_sources[0x19]	3834	1			T1	30		T3	4		T4	13
valid_sources[0x1a]	3405	1			T3	5		T4	15		T5	3
valid_sources[0x1b]	5220	1			T3	1		T9	8		T10	16
valid_sources[0x1c]	3341	1			T1	21		T9	15		T10	19
valid_sources[0x1d]	3618	1			T1	8		T7	2		T9	9
valid_sources[0x1e]	3986	1			T9	22		T10	19		T11	2
valid_sources[0x1f]	3580	1			T5	1		T9	19		T10	23
valid_sources[0x20]	3940	1			T1	6		T4	1		T9	13
valid_sources[0x21]	3688	1			T4	9		T9	8		T10	23
valid_sources[0x22]	3626	1			T4	3		T5	2		T9	10
valid_sources[0x23]	2960	1			T3	1		T9	7		T10	38
valid_sources[0x24]	3912	1			T1	10		T3	3		T9	8
valid_sources[0x25]	3563	1			T1	13		T3	2		T9	22
valid_sources[0x26]	4004	1			T3	6		T4	20		T9	12
valid_sources[0x27]	4092	1			T3	2		T9	8		T10	13
valid_sources[0x28]	3573	1			T3	4		T5	1		T9	10
valid_sources[0x29]	3468	1			T1	16		T3	3		T4	20
valid_sources[0x2a]	4994	1			T1	8		T3	1		T9	17
valid_sources[0x2b]	3675	1			T3	4		T9	10		T10	23
valid_sources[0x2c]	3943	1			T4	25		T9	9		T10	19
valid_sources[0x2d]	3459	1			T1	84		T4	1		T9	6
valid_sources[0x2e]	4353	1			T1	35		T3	2		T4	18
valid_sources[0x2f]	3952	1			T1	3		T9	12		T10	23
valid_sources[0x30]	4826	1			T3	2		T5	2		T9	17
valid_sources[0x31]	3892	1			T4	6		T9	8		T10	20
valid_sources[0x32]	3388	1			T2	1		T3	1		T4	34
valid_sources[0x33]	4265	1			T1	36		T9	7		T10	34
valid_sources[0x34]	4504	1			T1	82		T3	4		T9	5
valid_sources[0x35]	3866	1			T3	2		T5	1		T9	20
valid_sources[0x36]	3482	1			T3	6		T9	5		T10	24
valid_sources[0x37]	4389	1			T3	1		T9	15		T10	12
valid_sources[0x38]	4000	1			T1	10		T9	10		T10	20
valid_sources[0x39]	3395	1			T1	16		T9	9		T10	30
valid_sources[0x3a]	3914	1			T1	32		T3	3		T4	10
valid_sources[0x3b]	3972	1			T3	5		T5	11		T9	10
valid_sources[0x3c]	5989	1			T1	14		T9	6		T10	13
valid_sources[0x3d]	3280	1			T1	3		T4	4		T9	23
valid_sources[0x3e]	4514	1			T1	13		T3	1		T4	22
valid_sources[0x3f]	5601	1			T1	3		T4	4		T5	16
valid_sources[0x40]	4108	1			T1	3		T2	3		T3	1
valid_sources[0x41]	3502	1			T1	20		T4	2		T9	22
valid_sources[0x42]	4199	1			T1	1		T9	18		T10	33
valid_sources[0x43]	4042	1			T1	4		T4	17		T9	6
valid_sources[0x44]	3945	1			T1	69		T3	2		T9	9
valid_sources[0x45]	3208	1			T1	5		T3	1		T4	9
valid_sources[0x46]	4810	1			T4	13		T9	7		T10	16
valid_sources[0x47]	3701	1			T3	2		T5	5		T9	9
valid_sources[0x48]	3221	1			T4	3		T9	8		T10	42
valid_sources[0x49]	3813	1			T3	2		T9	5		T10	24
valid_sources[0x4a]	3379	1			T1	17		T3	3		T9	21
valid_sources[0x4b]	4119	1			T1	1		T3	1		T9	30
valid_sources[0x4c]	3272	1			T1	7		T4	4		T5	1
valid_sources[0x4d]	3442	1			T1	6		T3	1		T5	1
valid_sources[0x4e]	3780	1			T3	1		T4	7		T5	3
valid_sources[0x4f]	3898	1			T1	4		T3	2		T4	12
valid_sources[0x50]	6782	1			T9	13		T10	18		T11	3
valid_sources[0x51]	5389	1			T4	4		T9	15		T10	31
valid_sources[0x52]	3643	1			T4	8		T9	13		T10	22
valid_sources[0x53]	4087	1			T1	60		T5	11		T9	10
valid_sources[0x54]	3747	1			T5	4		T9	6		T10	25
valid_sources[0x55]	6928	1			T1	2		T9	12		T10	29
valid_sources[0x56]	3944	1			T4	3		T9	9		T10	12
valid_sources[0x57]	3179	1			T1	11		T9	14		T10	26
valid_sources[0x58]	4405	1			T2	1		T3	4		T4	4
valid_sources[0x59]	3696	1			T1	29		T4	4		T9	17
valid_sources[0x5a]	3596	1			T3	1		T9	24		T10	22
valid_sources[0x5b]	3263	1			T2	1		T9	14		T10	30
valid_sources[0x5c]	4123	1			T9	20		T10	30		T11	1
valid_sources[0x5d]	4024	1			T1	17		T3	2		T9	11
valid_sources[0x5e]	3345	1			T1	7		T3	4		T9	15
valid_sources[0x5f]	3149	1			T1	20		T9	10		T10	16
valid_sources[0x60]	2909	1			T1	9		T3	1		T4	1
valid_sources[0x61]	3257	1			T1	70		T3	1		T4	8
valid_sources[0x62]	3910	1			T1	3		T9	21		T10	32
valid_sources[0x63]	3549	1			T1	19		T9	13		T10	30
valid_sources[0x64]	3692	1			T9	19		T10	15		T42	1
valid_sources[0x65]	4361	1			T1	22		T3	1		T4	3
valid_sources[0x66]	4233	1			T1	5		T3	1		T9	9
valid_sources[0x67]	3715	1			T5	4		T9	6		T10	30
valid_sources[0x68]	3291	1			T1	68		T9	16		T10	17
valid_sources[0x69]	4011	1			T1	1		T5	3		T9	9
valid_sources[0x6a]	5572	1			T9	7		T10	20		T12	19
valid_sources[0x6b]	4904	1			T1	14		T9	9		T10	22
valid_sources[0x6c]	3603	1			T9	6		T10	51		T11	3
valid_sources[0x6d]	3191	1			T1	28		T4	32		T9	10
valid_sources[0x6e]	7264	1			T1	31		T3	1		T9	5
valid_sources[0x6f]	3457	1			T5	18		T9	8		T10	33
valid_sources[0x70]	3628	1			T1	47		T3	1		T4	11
valid_sources[0x71]	3608	1			T5	9		T9	18		T10	33
valid_sources[0x72]	3333	1			T1	28		T3	2		T4	27
valid_sources[0x73]	3948	1			T3	1		T5	6		T9	8
valid_sources[0x74]	4495	1			T1	15		T9	16		T10	21
valid_sources[0x75]	3082	1			T9	9		T10	11		T11	3
valid_sources[0x76]	3714	1			T1	138		T9	19		T10	25
valid_sources[0x77]	5161	1			T1	62		T3	1		T4	14
valid_sources[0x78]	5564	1			T1	15		T3	1		T9	10
valid_sources[0x79]	2879	1			T1	28		T3	2		T9	9
valid_sources[0x7a]	4109	1			T3	1		T9	5		T10	29
valid_sources[0x7b]	4248	1			T9	19		T10	9		T11	3
valid_sources[0x7c]	3619	1			T1	4		T9	16		T10	18
valid_sources[0x7d]	7641	1			T1	17		T9	22		T10	31
valid_sources[0x7e]	3277	1			T3	1		T9	20		T10	28
valid_sources[0x7f]	4299	1			T1	37		T9	13		T10	17
valid_sources[0x80]	3471	1			T3	5		T4	5		T9	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

255682

1

T1

816

T3

64

T4

253

values[0x0]

all_enables

biggest_size

82923

1

T1

235

T3

24

T4

68

values[0x1]

all_enables

biggest_size

44069

1

T1

109

T3

11

T4

38