Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T5,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57442479	9375	0	0
CascadeEffAonToRstPorAboveRise_A	57442479	9375	0	0
CascadeEffAonToRstPorIoAboveFall_A	55142810	9375	0	0
CascadeEffAonToRstPorIoAboveRise_A	55142810	9375	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27572448	9375	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27572448	9375	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13785689	9375	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13785689	9375	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27572355	9375	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27572355	9375	0	0
CascadeLcToLcAboveFall_A	57442479	22830	0	0
CascadeLcToLcAboveRise_A	57442479	22830	0	0
CascadeLcToLcAonAboveFall_A	1741030	22830	0	0
CascadeLcToLcAonAboveRise_A	1741030	22830	0	0
CascadeLcToLcShadowedAboveFall_A	57442479	22830	0	0
CascadeLcToLcShadowedAboveRise_A	57442479	22830	0	0
CascadePorToAonAboveFall_A	1741030	7423	0	0
CascadeSysToSysAboveFall_A	57442479	22830	0	0
CascadeSysToSysAboveRise_A	57442479	22830	0	0
ScanRstToAonRise_A	1741030	217	0	0
StablePorToAonRise_A	1741030	9375	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12227093	22830	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12227093	22830	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12227093	22830	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12227093	22830	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13785689	22830	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13785689	22830	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12227093	22830	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12227093	22830	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12227093	22830	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12227093	22830	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57442479	9375	0	0
T1	98740	20	0	0
T2	165397	541	0	0
T3	20794	1	0	0
T4	13092	1	0	0
T5	11127	2	0	0
T6	11498	2	0	0
T7	7082	1	0	0
T8	24384	8	0	0
T9	121362	27	0	0
T10	391466	41	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57442479	9375	0	0
T1	98740	20	0	0
T2	165397	541	0	0
T3	20794	1	0	0
T4	13092	1	0	0
T5	11127	2	0	0
T6	11498	2	0	0
T7	7082	1	0	0
T8	24384	8	0	0
T9	121362	27	0	0
T10	391466	41	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55142810	9375	0	0
T1	94747	20	0	0
T2	158775	541	0	0
T3	19962	1	0	0
T4	12567	1	0	0
T5	10683	2	0	0
T6	11039	2	0	0
T7	6799	1	0	0
T8	23406	8	0	0
T9	116538	27	0	0
T10	375781	41	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55142810	9375	0	0
T1	94747	20	0	0
T2	158775	541	0	0
T3	19962	1	0	0
T4	12567	1	0	0
T5	10683	2	0	0
T6	11039	2	0	0
T7	6799	1	0	0
T8	23406	8	0	0
T9	116538	27	0	0
T10	375781	41	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572448	9375	0	0
T1	47392	20	0	0
T2	793863	541	0	0
T3	9981	1	0	0
T4	6284	1	0	0
T5	5344	2	0	0
T6	5518	2	0	0
T7	3399	1	0	0
T8	11702	8	0	0
T9	58247	27	0	0
T10	187899	41	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572448	9375	0	0
T1	47392	20	0	0
T2	793863	541	0	0
T3	9981	1	0	0
T4	6284	1	0	0
T5	5344	2	0	0
T6	5518	2	0	0
T7	3399	1	0	0
T8	11702	8	0	0
T9	58247	27	0	0
T10	187899	41	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	9375	0	0
T1	23697	20	0	0
T2	396993	541	0	0
T3	4989	1	0	0
T4	3141	1	0	0
T5	2671	2	0	0
T6	2759	2	0	0
T7	1699	1	0	0
T8	5846	8	0	0
T9	29132	27	0	0
T10	93944	41	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	9375	0	0
T1	23697	20	0	0
T2	396993	541	0	0
T3	4989	1	0	0
T4	3141	1	0	0
T5	2671	2	0	0
T6	2759	2	0	0
T7	1699	1	0	0
T8	5846	8	0	0
T9	29132	27	0	0
T10	93944	41	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572355	9375	0	0
T1	47392	20	0	0
T2	793953	541	0	0
T3	9981	1	0	0
T4	6284	1	0	0
T5	5342	2	0	0
T6	5520	2	0	0
T7	3399	1	0	0
T8	11702	8	0	0
T9	58282	27	0	0
T10	187891	41	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572355	9375	0	0
T1	47392	20	0	0
T2	793953	541	0	0
T3	9981	1	0	0
T4	6284	1	0	0
T5	5342	2	0	0
T6	5520	2	0	0
T7	3399	1	0	0
T8	11702	8	0	0
T9	58282	27	0	0
T10	187891	41	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57442479	22830	0	0
T1	98740	63	0	0
T2	165397	541	0	0
T3	20794	15	0	0
T4	13092	1	0	0
T5	11127	6	0	0
T6	11498	6	0	0
T7	7082	1	0	0
T8	24384	8	0	0
T9	121362	102	0	0
T10	391466	106	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57442479	22830	0	0
T1	98740	63	0	0
T2	165397	541	0	0
T3	20794	15	0	0
T4	13092	1	0	0
T5	11127	6	0	0
T6	11498	6	0	0
T7	7082	1	0	0
T8	24384	8	0	0
T9	121362	102	0	0
T10	391466	106	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741030	22830	0	0
T1	3044	63	0	0
T2	49865	541	0	0
T3	622	15	0	0
T4	392	1	0	0
T5	333	6	0	0
T6	344	6	0	0
T7	212	1	0	0
T8	733	8	0	0
T9	3655	102	0	0
T10	11861	106	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741030	22830	0	0
T1	3044	63	0	0
T2	49865	541	0	0
T3	622	15	0	0
T4	392	1	0	0
T5	333	6	0	0
T6	344	6	0	0
T7	212	1	0	0
T8	733	8	0	0
T9	3655	102	0	0
T10	11861	106	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57442479	22830	0	0
T1	98740	63	0	0
T2	165397	541	0	0
T3	20794	15	0	0
T4	13092	1	0	0
T5	11127	6	0	0
T6	11498	6	0	0
T7	7082	1	0	0
T8	24384	8	0	0
T9	121362	102	0	0
T10	391466	106	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57442479	22830	0	0
T1	98740	63	0	0
T2	165397	541	0	0
T3	20794	15	0	0
T4	13092	1	0	0
T5	11127	6	0	0
T6	11498	6	0	0
T7	7082	1	0	0
T8	24384	8	0	0
T9	121362	102	0	0
T10	391466	106	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741030	7423	0	0
T1	3044	11	0	0
T2	49865	541	0	0
T3	622	1	0	0
T4	392	1	0	0
T5	333	1	0	0
T6	344	1	0	0
T7	212	1	0	0
T8	733	8	0	0
T9	3655	27	0	0
T10	11861	19	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57442479	22830	0	0
T1	98740	63	0	0
T2	165397	541	0	0
T3	20794	15	0	0
T4	13092	1	0	0
T5	11127	6	0	0
T6	11498	6	0	0
T7	7082	1	0	0
T8	24384	8	0	0
T9	121362	102	0	0
T10	391466	106	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57442479	22830	0	0
T1	98740	63	0	0
T2	165397	541	0	0
T3	20794	15	0	0
T4	13092	1	0	0
T5	11127	6	0	0
T6	11498	6	0	0
T7	7082	1	0	0
T8	24384	8	0	0
T9	121362	102	0	0
T10	391466	106	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741030	217	0	0
T10	11861	3	0	0
T11	754	0	0	0
T12	2619	1	0	0
T13	3188	0	0	0
T14	328	0	0	0
T15	382	0	0	0
T16	692	0	0	0
T25	1155	0	0	0
T26	732	0	0	0
T42	178	0	0	0
T52	0	6	0	0
T55	0	2	0	0
T75	0	1	0	0
T80	0	5	0	0
T81	0	1	0	0
T83	0	12	0	0
T87	0	1	0	0
T123	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741030	9375	0	0
T1	3044	20	0	0
T2	49865	541	0	0
T3	622	1	0	0
T4	392	1	0	0
T5	333	2	0	0
T6	344	2	0	0
T7	212	1	0	0
T8	733	8	0	0
T9	3655	27	0	0
T10	11861	41	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12227093	22830	0	0
T1	18286	63	0	0
T2	346999	541	0	0
T3	3966	15	0	0
T4	3122	1	0	0
T5	2523	6	0	0
T6	2516	6	0	0
T7	1632	1	0	0
T8	5689	8	0	0
T9	26164	102	0	0
T10	83567	106	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12227093	22830	0	0
T1	18286	63	0	0
T2	346999	541	0	0
T3	3966	15	0	0
T4	3122	1	0	0
T5	2523	6	0	0
T6	2516	6	0	0
T7	1632	1	0	0
T8	5689	8	0	0
T9	26164	102	0	0
T10	83567	106	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12227093	22830	0	0
T1	18286	63	0	0
T2	346999	541	0	0
T3	3966	15	0	0
T4	3122	1	0	0
T5	2523	6	0	0
T6	2516	6	0	0
T7	1632	1	0	0
T8	5689	8	0	0
T9	26164	102	0	0
T10	83567	106	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12227093	22830	0	0
T1	18286	63	0	0
T2	346999	541	0	0
T3	3966	15	0	0
T4	3122	1	0	0
T5	2523	6	0	0
T6	2516	6	0	0
T7	1632	1	0	0
T8	5689	8	0	0
T9	26164	102	0	0
T10	83567	106	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	22830	0	0
T1	23697	63	0	0
T2	396993	541	0	0
T3	4989	15	0	0
T4	3141	1	0	0
T5	2671	6	0	0
T6	2759	6	0	0
T7	1699	1	0	0
T8	5846	8	0	0
T9	29132	102	0	0
T10	93944	106	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	22830	0	0
T1	23697	63	0	0
T2	396993	541	0	0
T3	4989	15	0	0
T4	3141	1	0	0
T5	2671	6	0	0
T6	2759	6	0	0
T7	1699	1	0	0
T8	5846	8	0	0
T9	29132	102	0	0
T10	93944	106	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12227093	22830	0	0
T1	18286	63	0	0
T2	346999	541	0	0
T3	3966	15	0	0
T4	3122	1	0	0
T5	2523	6	0	0
T6	2516	6	0	0
T7	1632	1	0	0
T8	5689	8	0	0
T9	26164	102	0	0
T10	83567	106	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12227093	22830	0	0
T1	18286	63	0	0
T2	346999	541	0	0
T3	3966	15	0	0
T4	3122	1	0	0
T5	2523	6	0	0
T6	2516	6	0	0
T7	1632	1	0	0
T8	5689	8	0	0
T9	26164	102	0	0
T10	83567	106	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12227093	22830	0	0
T1	18286	63	0	0
T2	346999	541	0	0
T3	3966	15	0	0
T4	3122	1	0	0
T5	2523	6	0	0
T6	2516	6	0	0
T7	1632	1	0	0
T8	5689	8	0	0
T9	26164	102	0	0
T10	83567	106	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12227093	22830	0	0
T1	18286	63	0	0
T2	346999	541	0	0
T3	3966	15	0	0
T4	3122	1	0	0
T5	2523	6	0	0
T6	2516	6	0	0
T7	1632	1	0	0
T8	5689	8	0	0
T9	26164	102	0	0
T10	83567	106	0	0