Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T25
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T25
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T25
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T25
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T25
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13785689	14359	0	0
gen_assertions[0].RstEnOn_A	13785689	1072	0	0
gen_assertions[0].RstNOff_A	13785689	14359	0	0
gen_assertions[0].RstNOn_A	13785689	1072	0	0
gen_assertions[1].RstEnOff_A	55142810	13043	0	0
gen_assertions[1].RstEnOn_A	55142810	1007	0	0
gen_assertions[1].RstNOff_A	55142810	13043	0	0
gen_assertions[1].RstNOn_A	55142810	1007	0	0
gen_assertions[2].RstEnOff_A	27572448	13116	0	0
gen_assertions[2].RstEnOn_A	27572448	1050	0	0
gen_assertions[2].RstNOff_A	27572448	13116	0	0
gen_assertions[2].RstNOn_A	27572448	1050	0	0
gen_assertions[3].RstEnOff_A	27572355	13154	0	0
gen_assertions[3].RstEnOn_A	27572355	1074	0	0
gen_assertions[3].RstNOff_A	27572355	13154	0	0
gen_assertions[3].RstNOn_A	27572355	1074	0	0
gen_assertions[4].RstEnOff_A	1741030	22782	0	0
gen_assertions[4].RstEnOn_A	1741030	1152	0	0
gen_assertions[4].RstNOff_A	1741030	22782	0	0
gen_assertions[4].RstNOn_A	1741030	1152	0	0
gen_assertions[5].RstEnOff_A	13785689	14600	0	0
gen_assertions[5].RstEnOn_A	13785689	1186	0	0
gen_assertions[5].RstNOff_A	13785689	14600	0	0
gen_assertions[5].RstNOn_A	13785689	1186	0	0
gen_assertions[6].RstEnOff_A	13785689	14674	0	0
gen_assertions[6].RstEnOn_A	13785689	1253	0	0
gen_assertions[6].RstNOff_A	13785689	14674	0	0
gen_assertions[6].RstNOn_A	13785689	1253	0	0
gen_assertions[7].RstEnOff_A	13785689	14705	0	0
gen_assertions[7].RstEnOn_A	13785689	1294	0	0
gen_assertions[7].RstNOff_A	13785689	14705	0	0
gen_assertions[7].RstNOn_A	13785689	1294	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	14359	0	0
T1	23697	43	0	0
T2	396993	0	0	0
T3	4989	14	0	0
T4	3141	5	0	0
T5	2671	4	0	0
T6	2759	4	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	75	0	0
T10	93944	72	0	0
T11	0	4	0	0
T12	0	38	0	0
T13	0	32	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	1072	0	0
T3	4989	3	0	0
T4	3141	5	0	0
T5	2671	0	0	0
T6	2759	0	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	0	0	0
T10	93944	7	0	0
T11	6043	0	0	0
T25	0	8	0	0
T31	0	3	0	0
T32	0	7	0	0
T42	1430	0	0	0
T50	0	7	0	0
T52	0	20	0	0
T53	0	1	0	0
T74	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	14359	0	0
T1	23697	43	0	0
T2	396993	0	0	0
T3	4989	14	0	0
T4	3141	5	0	0
T5	2671	4	0	0
T6	2759	4	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	75	0	0
T10	93944	72	0	0
T11	0	4	0	0
T12	0	38	0	0
T13	0	32	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	1072	0	0
T3	4989	3	0	0
T4	3141	5	0	0
T5	2671	0	0	0
T6	2759	0	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	0	0	0
T10	93944	7	0	0
T11	6043	0	0	0
T25	0	8	0	0
T31	0	3	0	0
T32	0	7	0	0
T42	1430	0	0	0
T50	0	7	0	0
T52	0	20	0	0
T53	0	1	0	0
T74	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55142810	13043	0	0
T1	94747	35	0	0
T2	158775	0	0	0
T3	19962	12	0	0
T4	12567	2	0	0
T5	10683	4	0	0
T6	11039	4	0	0
T7	6799	0	0	0
T8	23406	0	0	0
T9	116538	70	0	0
T10	375781	69	0	0
T11	0	2	0	0
T12	0	36	0	0
T13	0	32	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55142810	1007	0	0
T4	12567	2	0	0
T5	10683	0	0	0
T6	11039	0	0	0
T7	6799	0	0	0
T8	23406	0	0	0
T9	116538	0	0	0
T10	375781	9	0	0
T11	24174	0	0	0
T12	81413	0	0	0
T25	0	8	0	0
T31	0	4	0	0
T32	0	8	0	0
T42	5729	0	0	0
T50	0	5	0	0
T52	0	19	0	0
T53	0	2	0	0
T55	0	30	0	0
T75	0	9	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55142810	13043	0	0
T1	94747	35	0	0
T2	158775	0	0	0
T3	19962	12	0	0
T4	12567	2	0	0
T5	10683	4	0	0
T6	11039	4	0	0
T7	6799	0	0	0
T8	23406	0	0	0
T9	116538	70	0	0
T10	375781	69	0	0
T11	0	2	0	0
T12	0	36	0	0
T13	0	32	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55142810	1007	0	0
T4	12567	2	0	0
T5	10683	0	0	0
T6	11039	0	0	0
T7	6799	0	0	0
T8	23406	0	0	0
T9	116538	0	0	0
T10	375781	9	0	0
T11	24174	0	0	0
T12	81413	0	0	0
T25	0	8	0	0
T31	0	4	0	0
T32	0	8	0	0
T42	5729	0	0	0
T50	0	5	0	0
T52	0	19	0	0
T53	0	2	0	0
T55	0	30	0	0
T75	0	9	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572448	13116	0	0
T1	47392	35	0	0
T2	793863	0	0	0
T3	9981	12	0	0
T4	6284	7	0	0
T5	5344	4	0	0
T6	5518	4	0	0
T7	3399	0	0	0
T8	11702	0	0	0
T9	58247	70	0	0
T10	187899	68	0	0
T11	0	2	0	0
T12	0	36	0	0
T13	0	32	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572448	1050	0	0
T4	6284	7	0	0
T5	5344	0	0	0
T6	5518	0	0	0
T7	3399	0	0	0
T8	11702	0	0	0
T9	58247	0	0	0
T10	187899	8	0	0
T11	12087	0	0	0
T12	40710	0	0	0
T25	0	9	0	0
T31	0	5	0	0
T32	0	5	0	0
T42	2864	0	0	0
T50	0	9	0	0
T52	0	22	0	0
T53	0	6	0	0
T55	0	27	0	0
T74	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572448	13116	0	0
T1	47392	35	0	0
T2	793863	0	0	0
T3	9981	12	0	0
T4	6284	7	0	0
T5	5344	4	0	0
T6	5518	4	0	0
T7	3399	0	0	0
T8	11702	0	0	0
T9	58247	70	0	0
T10	187899	68	0	0
T11	0	2	0	0
T12	0	36	0	0
T13	0	32	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572448	1050	0	0
T4	6284	7	0	0
T5	5344	0	0	0
T6	5518	0	0	0
T7	3399	0	0	0
T8	11702	0	0	0
T9	58247	0	0	0
T10	187899	8	0	0
T11	12087	0	0	0
T12	40710	0	0	0
T25	0	9	0	0
T31	0	5	0	0
T32	0	5	0	0
T42	2864	0	0	0
T50	0	9	0	0
T52	0	22	0	0
T53	0	6	0	0
T55	0	27	0	0
T74	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572355	13154	0	0
T1	47392	35	0	0
T2	793953	0	0	0
T3	9981	12	0	0
T4	6284	9	0	0
T5	5342	4	0	0
T6	5520	5	0	0
T7	3399	0	0	0
T8	11702	0	0	0
T9	58282	70	0	0
T10	187891	67	0	0
T11	0	2	0	0
T12	0	36	0	0
T13	0	32	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572355	1074	0	0
T4	6284	9	0	0
T5	5342	0	0	0
T6	5520	1	0	0
T7	3399	0	0	0
T8	11702	0	0	0
T9	58282	0	0	0
T10	187891	7	0	0
T11	12086	0	0	0
T12	40716	0	0	0
T25	0	8	0	0
T31	0	5	0	0
T32	0	9	0	0
T42	2864	0	0	0
T50	0	9	0	0
T52	0	21	0	0
T53	0	6	0	0
T55	0	25	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572355	13154	0	0
T1	47392	35	0	0
T2	793953	0	0	0
T3	9981	12	0	0
T4	6284	9	0	0
T5	5342	4	0	0
T6	5520	5	0	0
T7	3399	0	0	0
T8	11702	0	0	0
T9	58282	70	0	0
T10	187891	67	0	0
T11	0	2	0	0
T12	0	36	0	0
T13	0	32	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27572355	1074	0	0
T4	6284	9	0	0
T5	5342	0	0	0
T6	5520	1	0	0
T7	3399	0	0	0
T8	11702	0	0	0
T9	58282	0	0	0
T10	187891	7	0	0
T11	12086	0	0	0
T12	40716	0	0	0
T25	0	8	0	0
T31	0	5	0	0
T32	0	9	0	0
T42	2864	0	0	0
T50	0	9	0	0
T52	0	21	0	0
T53	0	6	0	0
T55	0	25	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741030	22782	0	0
T1	3044	63	0	0
T2	49865	541	0	0
T3	622	15	0	0
T4	392	9	0	0
T5	333	6	0	0
T6	344	6	0	0
T7	212	1	0	0
T8	733	3	0	0
T9	3655	76	0	0
T10	11861	112	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741030	1152	0	0
T4	392	8	0	0
T5	333	0	0	0
T6	344	0	0	0
T7	212	0	0	0
T8	733	0	0	0
T9	3655	0	0	0
T10	11861	8	0	0
T11	754	0	0	0
T12	2619	0	0	0
T25	0	11	0	0
T31	0	6	0	0
T32	0	8	0	0
T42	178	0	0	0
T50	0	7	0	0
T52	0	25	0	0
T53	0	8	0	0
T54	0	1	0	0
T74	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741030	22782	0	0
T1	3044	63	0	0
T2	49865	541	0	0
T3	622	15	0	0
T4	392	9	0	0
T5	333	6	0	0
T6	344	6	0	0
T7	212	1	0	0
T8	733	3	0	0
T9	3655	76	0	0
T10	11861	112	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741030	1152	0	0
T4	392	8	0	0
T5	333	0	0	0
T6	344	0	0	0
T7	212	0	0	0
T8	733	0	0	0
T9	3655	0	0	0
T10	11861	8	0	0
T11	754	0	0	0
T12	2619	0	0	0
T25	0	11	0	0
T31	0	6	0	0
T32	0	8	0	0
T42	178	0	0	0
T50	0	7	0	0
T52	0	25	0	0
T53	0	8	0	0
T54	0	1	0	0
T74	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	14600	0	0
T1	23697	43	0	0
T2	396993	0	0	0
T3	4989	14	0	0
T4	3141	10	0	0
T5	2671	4	0	0
T6	2759	5	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	75	0	0
T10	93944	74	0	0
T11	0	4	0	0
T12	0	38	0	0
T13	0	32	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	1186	0	0
T4	3141	10	0	0
T5	2671	0	0	0
T6	2759	1	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	0	0	0
T10	93944	9	0	0
T11	6043	0	0	0
T12	20355	0	0	0
T25	0	13	0	0
T31	0	7	0	0
T32	0	10	0	0
T42	1430	0	0	0
T50	0	10	0	0
T52	0	17	0	0
T53	0	8	0	0
T55	0	29	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	14600	0	0
T1	23697	43	0	0
T2	396993	0	0	0
T3	4989	14	0	0
T4	3141	10	0	0
T5	2671	4	0	0
T6	2759	5	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	75	0	0
T10	93944	74	0	0
T11	0	4	0	0
T12	0	38	0	0
T13	0	32	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	1186	0	0
T4	3141	10	0	0
T5	2671	0	0	0
T6	2759	1	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	0	0	0
T10	93944	9	0	0
T11	6043	0	0	0
T12	20355	0	0	0
T25	0	13	0	0
T31	0	7	0	0
T32	0	10	0	0
T42	1430	0	0	0
T50	0	10	0	0
T52	0	17	0	0
T53	0	8	0	0
T55	0	29	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	14674	0	0
T1	23697	43	0	0
T2	396993	0	0	0
T3	4989	14	0	0
T4	3141	10	0	0
T5	2671	4	0	0
T6	2759	4	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	75	0	0
T10	93944	74	0	0
T11	0	4	0	0
T12	0	38	0	0
T13	0	32	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	1253	0	0
T4	3141	10	0	0
T5	2671	0	0	0
T6	2759	0	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	0	0	0
T10	93944	9	0	0
T11	6043	0	0	0
T12	20355	0	0	0
T25	0	13	0	0
T31	0	7	0	0
T32	0	6	0	0
T42	1430	0	0	0
T50	0	13	0	0
T52	0	26	0	0
T53	0	10	0	0
T54	0	1	0	0
T55	0	25	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	14674	0	0
T1	23697	43	0	0
T2	396993	0	0	0
T3	4989	14	0	0
T4	3141	10	0	0
T5	2671	4	0	0
T6	2759	4	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	75	0	0
T10	93944	74	0	0
T11	0	4	0	0
T12	0	38	0	0
T13	0	32	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	1253	0	0
T4	3141	10	0	0
T5	2671	0	0	0
T6	2759	0	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	0	0	0
T10	93944	9	0	0
T11	6043	0	0	0
T12	20355	0	0	0
T25	0	13	0	0
T31	0	7	0	0
T32	0	6	0	0
T42	1430	0	0	0
T50	0	13	0	0
T52	0	26	0	0
T53	0	10	0	0
T54	0	1	0	0
T55	0	25	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	14705	0	0
T1	23697	43	0	0
T2	396993	0	0	0
T3	4989	14	0	0
T4	3141	12	0	0
T5	2671	4	0	0
T6	2759	4	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	75	0	0
T10	93944	74	0	0
T11	0	4	0	0
T12	0	38	0	0
T13	0	32	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	1294	0	0
T4	3141	12	0	0
T5	2671	0	0	0
T6	2759	0	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	0	0	0
T10	93944	9	0	0
T11	6043	0	0	0
T12	20355	0	0	0
T25	0	16	0	0
T31	0	8	0	0
T32	0	8	0	0
T42	1430	0	0	0
T50	0	15	0	0
T52	0	20	0	0
T53	0	11	0	0
T55	0	22	0	0
T75	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	14705	0	0
T1	23697	43	0	0
T2	396993	0	0	0
T3	4989	14	0	0
T4	3141	12	0	0
T5	2671	4	0	0
T6	2759	4	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	75	0	0
T10	93944	74	0	0
T11	0	4	0	0
T12	0	38	0	0
T13	0	32	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13785689	1294	0	0
T4	3141	12	0	0
T5	2671	0	0	0
T6	2759	0	0	0
T7	1699	0	0	0
T8	5846	0	0	0
T9	29132	0	0	0
T10	93944	9	0	0
T11	6043	0	0	0
T12	20355	0	0	0
T25	0	16	0	0
T31	0	8	0	0
T32	0	8	0	0
T42	1430	0	0	0
T50	0	15	0	0
T52	0	20	0	0
T53	0	11	0	0
T55	0	22	0	0
T75	0	8	0	0