Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12933026	7937	0	0
alert_regwen_rd_A	12933026	4079	0	0
cpu_regwen_rd_A	12933026	3966	0	0
sw_rst_ctrl_n_0_rd_A	12933026	8969	0	0
sw_rst_ctrl_n_1_rd_A	12933026	9091	0	0
sw_rst_ctrl_n_2_rd_A	12933026	9123	0	0
sw_rst_ctrl_n_3_rd_A	12933026	9423	0	0
sw_rst_ctrl_n_4_rd_A	12933026	8947	0	0
sw_rst_ctrl_n_5_rd_A	12933026	9234	0	0
sw_rst_ctrl_n_6_rd_A	12933026	9229	0	0
sw_rst_ctrl_n_7_rd_A	12933026	9267	0	0
sw_rst_regwen_0_rd_A	12933026	4671	0	0
sw_rst_regwen_1_rd_A	12933026	4437	0	0
sw_rst_regwen_2_rd_A	12933026	4768	0	0
sw_rst_regwen_3_rd_A	12933026	4667	0	0
sw_rst_regwen_4_rd_A	12933026	4651	0	0
sw_rst_regwen_5_rd_A	12933026	4568	0	0
sw_rst_regwen_6_rd_A	12933026	4663	0	0
sw_rst_regwen_7_rd_A	12933026	4727	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	7937	0	0
T60	4186	15	0	0
T64	3297	339	0	0
T65	12123	525	0	0
T66	3325	58	0	0
T67	4418	297	0	0
T70	3316	10	0	0
T71	4436	16	0	0
T76	25828	6	0	0
T77	2170	8	0	0
T79	19984	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	4079	0	0
T10	83567	145	0	0
T11	5663	0	0	0
T12	15574	0	0	0
T13	21774	0	0	0
T14	2382	0	0	0
T15	3006	0	0	0
T16	5408	0	0	0
T25	9203	0	0	0
T26	5685	0	0	0
T27	0	53	0	0
T42	1341	0	0	0
T80	0	444	0	0
T82	0	65	0	0
T85	0	40	0	0
T87	0	50	0	0
T117	0	29	0	0
T118	0	83	0	0
T119	0	297	0	0
T120	0	19	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	3966	0	0
T10	83567	147	0	0
T11	5663	0	0	0
T12	15574	0	0	0
T13	21774	0	0	0
T14	2382	0	0	0
T15	3006	0	0	0
T16	5408	0	0	0
T25	9203	0	0	0
T26	5685	0	0	0
T27	0	61	0	0
T42	1341	0	0	0
T80	0	422	0	0
T82	0	60	0	0
T85	0	43	0	0
T87	0	35	0	0
T117	0	37	0	0
T118	0	30	0	0
T119	0	341	0	0
T120	0	31	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	8969	0	0
T3	3966	55	0	0
T4	3122	0	0	0
T5	2523	0	0	0
T6	2516	0	0	0
T7	1632	0	0	0
T8	5689	0	0	0
T9	26164	0	0	0
T10	83567	247	0	0
T11	5663	13	0	0
T27	0	35	0	0
T31	0	143	0	0
T32	0	91	0	0
T42	1341	0	0	0
T50	0	149	0	0
T80	0	671	0	0
T121	0	9	0	0
T122	0	17	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	9091	0	0
T3	3966	21	0	0
T4	3122	0	0	0
T5	2523	0	0	0
T6	2516	0	0	0
T7	1632	0	0	0
T8	5689	0	0	0
T9	26164	0	0	0
T10	83567	225	0	0
T11	5663	8	0	0
T27	0	58	0	0
T31	0	157	0	0
T32	0	65	0	0
T42	1341	0	0	0
T50	0	103	0	0
T80	0	657	0	0
T121	0	10	0	0
T122	0	2	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	9123	0	0
T3	3966	37	0	0
T4	3122	0	0	0
T5	2523	0	0	0
T6	2516	0	0	0
T7	1632	0	0	0
T8	5689	0	0	0
T9	26164	0	0	0
T10	83567	281	0	0
T11	5663	14	0	0
T27	0	69	0	0
T31	0	130	0	0
T32	0	61	0	0
T42	1341	0	0	0
T50	0	139	0	0
T80	0	647	0	0
T121	0	6	0	0
T122	0	15	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	9423	0	0
T3	3966	17	0	0
T4	3122	0	0	0
T5	2523	0	0	0
T6	2516	0	0	0
T7	1632	0	0	0
T8	5689	0	0	0
T9	26164	0	0	0
T10	83567	272	0	0
T11	5663	8	0	0
T27	0	40	0	0
T31	0	156	0	0
T32	0	46	0	0
T42	1341	0	0	0
T50	0	146	0	0
T80	0	625	0	0
T121	0	23	0	0
T122	0	19	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	8947	0	0
T3	3966	17	0	0
T4	3122	0	0	0
T5	2523	0	0	0
T6	2516	0	0	0
T7	1632	0	0	0
T8	5689	0	0	0
T9	26164	0	0	0
T10	83567	248	0	0
T11	5663	13	0	0
T27	0	57	0	0
T31	0	118	0	0
T32	0	62	0	0
T42	1341	0	0	0
T50	0	81	0	0
T80	0	633	0	0
T121	0	26	0	0
T122	0	5	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	9234	0	0
T3	3966	25	0	0
T4	3122	0	0	0
T5	2523	0	0	0
T6	2516	0	0	0
T7	1632	0	0	0
T8	5689	0	0	0
T9	26164	0	0	0
T10	83567	256	0	0
T11	5663	16	0	0
T27	0	56	0	0
T31	0	152	0	0
T32	0	74	0	0
T42	1341	0	0	0
T50	0	101	0	0
T80	0	647	0	0
T121	0	11	0	0
T122	0	8	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	9229	0	0
T3	3966	38	0	0
T4	3122	0	0	0
T5	2523	0	0	0
T6	2516	0	0	0
T7	1632	0	0	0
T8	5689	0	0	0
T9	26164	0	0	0
T10	83567	255	0	0
T11	5663	6	0	0
T27	0	41	0	0
T31	0	123	0	0
T32	0	47	0	0
T42	1341	0	0	0
T50	0	97	0	0
T80	0	707	0	0
T121	0	7	0	0
T122	0	12	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	9267	0	0
T3	3966	20	0	0
T4	3122	0	0	0
T5	2523	0	0	0
T6	2516	0	0	0
T7	1632	0	0	0
T8	5689	0	0	0
T9	26164	0	0	0
T10	83567	265	0	0
T11	5663	11	0	0
T27	0	62	0	0
T31	0	144	0	0
T32	0	105	0	0
T42	1341	0	0	0
T50	0	116	0	0
T80	0	659	0	0
T121	0	10	0	0
T122	0	8	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	4671	0	0
T10	83567	133	0	0
T11	5663	4	0	0
T12	15574	0	0	0
T13	21774	0	0	0
T14	2382	0	0	0
T15	3006	0	0	0
T16	5408	0	0	0
T25	9203	0	0	0
T26	5685	0	0	0
T27	0	60	0	0
T31	0	34	0	0
T42	1341	0	0	0
T50	0	14	0	0
T80	0	407	0	0
T82	0	85	0	0
T87	0	64	0	0
T121	0	11	0	0
T122	0	8	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	4437	0	0
T10	83567	138	0	0
T11	5663	12	0	0
T12	15574	0	0	0
T13	21774	0	0	0
T14	2382	0	0	0
T15	3006	0	0	0
T16	5408	0	0	0
T25	9203	0	0	0
T26	5685	0	0	0
T27	0	45	0	0
T31	0	28	0	0
T42	1341	0	0	0
T50	0	34	0	0
T80	0	476	0	0
T82	0	81	0	0
T87	0	41	0	0
T121	0	12	0	0
T122	0	12	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	4768	0	0
T10	83567	141	0	0
T11	5663	10	0	0
T12	15574	0	0	0
T13	21774	0	0	0
T14	2382	0	0	0
T15	3006	0	0	0
T16	5408	0	0	0
T25	9203	0	0	0
T26	5685	0	0	0
T27	0	43	0	0
T31	0	48	0	0
T42	1341	0	0	0
T50	0	14	0	0
T80	0	508	0	0
T82	0	62	0	0
T87	0	79	0	0
T121	0	10	0	0
T122	0	6	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	4667	0	0
T10	83567	136	0	0
T11	5663	8	0	0
T12	15574	0	0	0
T13	21774	0	0	0
T14	2382	0	0	0
T15	3006	0	0	0
T16	5408	0	0	0
T25	9203	0	0	0
T26	5685	0	0	0
T27	0	53	0	0
T31	0	38	0	0
T42	1341	0	0	0
T50	0	20	0	0
T80	0	523	0	0
T82	0	96	0	0
T87	0	41	0	0
T121	0	9	0	0
T122	0	9	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	4651	0	0
T10	83567	133	0	0
T11	5663	7	0	0
T12	15574	0	0	0
T13	21774	0	0	0
T14	2382	0	0	0
T15	3006	0	0	0
T16	5408	0	0	0
T25	9203	0	0	0
T26	5685	0	0	0
T27	0	81	0	0
T31	0	41	0	0
T42	1341	0	0	0
T50	0	31	0	0
T80	0	490	0	0
T82	0	74	0	0
T87	0	23	0	0
T121	0	7	0	0
T122	0	6	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	4568	0	0
T10	83567	154	0	0
T11	5663	18	0	0
T12	15574	0	0	0
T13	21774	0	0	0
T14	2382	0	0	0
T15	3006	0	0	0
T16	5408	0	0	0
T25	9203	0	0	0
T26	5685	0	0	0
T27	0	67	0	0
T31	0	36	0	0
T42	1341	0	0	0
T50	0	8	0	0
T80	0	445	0	0
T82	0	80	0	0
T87	0	32	0	0
T121	0	2	0	0
T122	0	11	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	4663	0	0
T10	83567	146	0	0
T11	5663	12	0	0
T12	15574	0	0	0
T13	21774	0	0	0
T14	2382	0	0	0
T15	3006	0	0	0
T16	5408	0	0	0
T25	9203	0	0	0
T26	5685	0	0	0
T27	0	52	0	0
T31	0	30	0	0
T42	1341	0	0	0
T50	0	6	0	0
T80	0	411	0	0
T82	0	82	0	0
T87	0	54	0	0
T121	0	4	0	0
T122	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12933026	4727	0	0
T10	83567	123	0	0
T11	5663	5	0	0
T12	15574	0	0	0
T13	21774	0	0	0
T14	2382	0	0	0
T15	3006	0	0	0
T16	5408	0	0	0
T25	9203	0	0	0
T26	5685	0	0	0
T27	0	38	0	0
T31	0	33	0	0
T42	1341	0	0	0
T50	0	23	0	0
T80	0	511	0	0
T82	0	81	0	0
T87	0	58	0	0
T121	0	9	0	0
T122	0	11	0	0