Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	590200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

355341

1

T1

5873

T5

843

T7

128

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	504180	1			T1	8861		T2	1		T3	1
values[0x0]	220156	1			T1	3523		T5	505		T7	86
values[0x1]	221205	1			T1	3418		T5	450		T7	107

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	495306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

450235

1

T1

7464

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4250	1			T1	47		T11	8		T12	12
valid_sources[0x01]	6361	1			T1	46		T8	3		T9	1
valid_sources[0x02]	3901	1			T1	69		T11	11		T12	16
valid_sources[0x03]	3687	1			T1	44		T8	3		T11	4
valid_sources[0x04]	3302	1			T1	56		T8	1		T11	1
valid_sources[0x05]	6500	1			T1	50		T8	2		T11	2
valid_sources[0x06]	3665	1			T1	41		T8	2		T11	8
valid_sources[0x07]	2799	1			T1	93		T8	3		T11	3
valid_sources[0x08]	3944	1			T1	52		T8	3		T12	13
valid_sources[0x09]	4214	1			T1	56		T5	112		T8	1
valid_sources[0x0a]	3155	1			T1	55		T11	8		T12	20
valid_sources[0x0b]	3348	1			T1	56		T8	5		T11	6
valid_sources[0x0c]	3112	1			T1	63		T8	1		T11	7
valid_sources[0x0d]	3654	1			T1	70		T5	141		T11	3
valid_sources[0x0e]	3317	1			T1	71		T8	3		T10	19
valid_sources[0x0f]	4584	1			T1	73		T5	243		T8	4
valid_sources[0x10]	4100	1			T1	55		T8	3		T11	7
valid_sources[0x11]	3479	1			T1	48		T8	2		T11	9
valid_sources[0x12]	3460	1			T1	54		T8	1		T11	4
valid_sources[0x13]	3856	1			T1	70		T5	2		T8	2
valid_sources[0x14]	3262	1			T1	66		T11	8		T12	10
valid_sources[0x15]	5402	1			T1	43		T8	1		T11	10
valid_sources[0x16]	3626	1			T1	52		T5	13		T8	2
valid_sources[0x17]	3429	1			T1	69		T3	1		T11	4
valid_sources[0x18]	3464	1			T1	54		T8	3		T11	2
valid_sources[0x19]	3808	1			T1	73		T8	1		T11	8
valid_sources[0x1a]	3560	1			T1	60		T8	1		T11	2
valid_sources[0x1b]	3177	1			T1	53		T8	1		T11	10
valid_sources[0x1c]	3183	1			T1	63		T8	3		T11	3
valid_sources[0x1d]	3800	1			T1	48		T8	5		T11	3
valid_sources[0x1e]	3953	1			T1	57		T8	1		T11	4
valid_sources[0x1f]	6630	1			T1	47		T8	1		T11	6
valid_sources[0x20]	2811	1			T1	53		T8	2		T11	7
valid_sources[0x21]	2931	1			T1	68		T8	4		T11	1
valid_sources[0x22]	3278	1			T1	42		T5	2		T8	2
valid_sources[0x23]	3364	1			T1	70		T5	6		T8	1
valid_sources[0x24]	2994	1			T1	52		T11	3		T12	5
valid_sources[0x25]	3592	1			T1	78		T5	68		T12	12
valid_sources[0x26]	4691	1			T1	45		T11	3		T12	10
valid_sources[0x27]	3287	1			T1	85		T8	3		T11	3
valid_sources[0x28]	4852	1			T1	64		T8	1		T12	7
valid_sources[0x29]	3846	1			T1	64		T11	7		T12	8
valid_sources[0x2a]	3543	1			T1	58		T8	2		T11	6
valid_sources[0x2b]	3648	1			T1	51		T11	8		T12	6
valid_sources[0x2c]	6282	1			T1	69		T12	12		T22	21
valid_sources[0x2d]	3327	1			T1	62		T8	1		T11	1
valid_sources[0x2e]	3792	1			T1	62		T5	8		T8	1
valid_sources[0x2f]	2810	1			T1	65		T11	3		T12	14
valid_sources[0x30]	3209	1			T1	54		T12	8		T21	4
valid_sources[0x31]	3824	1			T1	64		T8	4		T12	8
valid_sources[0x32]	4114	1			T1	58		T11	12		T12	15
valid_sources[0x33]	4844	1			T1	59		T8	4		T12	14
valid_sources[0x34]	3568	1			T1	49		T11	4		T12	11
valid_sources[0x35]	3031	1			T1	56		T8	4		T11	2
valid_sources[0x36]	3120	1			T1	69		T11	1		T12	9
valid_sources[0x37]	3486	1			T1	41		T8	1		T12	18
valid_sources[0x38]	3679	1			T1	50		T8	1		T12	10
valid_sources[0x39]	5852	1			T1	53		T5	374		T8	2
valid_sources[0x3a]	3751	1			T1	53		T8	2		T12	12
valid_sources[0x3b]	4194	1			T1	78		T8	1		T11	2
valid_sources[0x3c]	2692	1			T1	58		T8	2		T11	4
valid_sources[0x3d]	3580	1			T1	47		T8	1		T12	12
valid_sources[0x3e]	3202	1			T1	52		T8	2		T11	6
valid_sources[0x3f]	2698	1			T1	87		T8	3		T11	4
valid_sources[0x40]	3474	1			T1	63		T11	1		T12	16
valid_sources[0x41]	3123	1			T1	57		T8	2		T12	4
valid_sources[0x42]	4687	1			T1	63		T7	379		T11	10
valid_sources[0x43]	6394	1			T1	63		T8	2		T11	2
valid_sources[0x44]	3576	1			T1	59		T11	19		T12	12
valid_sources[0x45]	3938	1			T1	75		T8	3		T11	7
valid_sources[0x46]	4312	1			T1	48		T8	2		T12	14
valid_sources[0x47]	5575	1			T1	52		T11	1		T12	8
valid_sources[0x48]	3625	1			T1	61		T11	1		T12	5
valid_sources[0x49]	3397	1			T1	62		T8	1		T12	4
valid_sources[0x4a]	2907	1			T1	63		T11	3		T12	16
valid_sources[0x4b]	3709	1			T1	62		T8	5		T11	3
valid_sources[0x4c]	2665	1			T1	60		T11	2		T12	6
valid_sources[0x4d]	2678	1			T1	79		T8	2		T12	14
valid_sources[0x4e]	3437	1			T1	72		T11	5		T12	13
valid_sources[0x4f]	3254	1			T1	62		T8	1		T12	12
valid_sources[0x50]	3146	1			T1	64		T11	7		T12	6
valid_sources[0x51]	4391	1			T1	67		T8	2		T11	11
valid_sources[0x52]	5310	1			T1	64		T8	2		T11	4
valid_sources[0x53]	3486	1			T1	70		T8	4		T11	3
valid_sources[0x54]	2843	1			T1	66		T8	2		T84	1
valid_sources[0x55]	3176	1			T1	57		T8	1		T11	2
valid_sources[0x56]	3088	1			T1	73		T11	9		T12	11
valid_sources[0x57]	3088	1			T1	70		T8	6		T11	2
valid_sources[0x58]	4937	1			T1	60		T8	2		T11	3
valid_sources[0x59]	3394	1			T1	71		T11	8		T12	5
valid_sources[0x5a]	3780	1			T1	66		T11	1		T12	7
valid_sources[0x5b]	3908	1			T1	58		T8	1		T11	6
valid_sources[0x5c]	3623	1			T1	71		T8	1		T11	8
valid_sources[0x5d]	4162	1			T1	52		T8	2		T11	4
valid_sources[0x5e]	3424	1			T1	45		T8	1		T11	8
valid_sources[0x5f]	3400	1			T1	58		T8	4		T12	16
valid_sources[0x60]	3828	1			T1	66		T8	1		T11	4
valid_sources[0x61]	2861	1			T1	61		T8	2		T12	12
valid_sources[0x62]	3196	1			T1	49		T8	2		T11	5
valid_sources[0x63]	3234	1			T1	50		T8	1		T11	1
valid_sources[0x64]	3993	1			T1	61		T4	1		T8	1
valid_sources[0x65]	6129	1			T1	64		T8	1		T11	5
valid_sources[0x66]	3666	1			T1	77		T8	4		T11	1
valid_sources[0x67]	4528	1			T1	55		T8	1		T11	3
valid_sources[0x68]	4979	1			T1	59		T11	3		T12	17
valid_sources[0x69]	2951	1			T1	68		T11	3		T12	12
valid_sources[0x6a]	3907	1			T1	71		T8	1		T11	2
valid_sources[0x6b]	3655	1			T1	44		T8	4		T12	6
valid_sources[0x6c]	3213	1			T1	60		T8	3		T11	1
valid_sources[0x6d]	3684	1			T1	72		T8	1		T12	15
valid_sources[0x6e]	3194	1			T1	52		T11	6		T12	9
valid_sources[0x6f]	3614	1			T1	57		T8	3		T11	7
valid_sources[0x70]	3297	1			T1	72		T5	113		T8	2
valid_sources[0x71]	3802	1			T1	67		T11	6		T12	3
valid_sources[0x72]	3744	1			T1	57		T8	2		T11	5
valid_sources[0x73]	3236	1			T1	68		T8	1		T11	2
valid_sources[0x74]	3092	1			T1	67		T8	1		T11	8
valid_sources[0x75]	7078	1			T1	75		T8	3		T11	2
valid_sources[0x76]	3439	1			T1	74		T8	1		T11	1
valid_sources[0x77]	3559	1			T1	64		T8	3		T11	1
valid_sources[0x78]	3740	1			T1	60		T5	354		T8	8
valid_sources[0x79]	3319	1			T1	53		T8	2		T11	1
valid_sources[0x7a]	3346	1			T1	63		T11	1		T12	12
valid_sources[0x7b]	3922	1			T1	61		T12	10		T21	2
valid_sources[0x7c]	3142	1			T1	52		T12	13		T21	4
valid_sources[0x7d]	4482	1			T1	61		T8	3		T11	4
valid_sources[0x7e]	5440	1			T1	59		T11	1		T12	5
valid_sources[0x7f]	5023	1			T1	61		T8	6		T11	5
valid_sources[0x80]	4666	1			T1	47		T5	112		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

236390

1

T1

4146

T5

589

T7

84

values[0x0]

all_enables

biggest_size

77107

1

T1

1180

T5

180

T7

24

values[0x1]

all_enables

biggest_size

41844

1

T1

547

T5

74

T7

20