Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T5,T7

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52871501	8809	0	0
CascadeEffAonToRstPorAboveRise_A	52871501	8809	0	0
CascadeEffAonToRstPorIoAboveFall_A	50755042	8809	0	0
CascadeEffAonToRstPorIoAboveRise_A	50755042	8809	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25378534	8809	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25378534	8809	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12688937	8809	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12688937	8809	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25378131	8809	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25378131	8809	0	0
CascadeLcToLcAboveFall_A	52871501	21373	0	0
CascadeLcToLcAboveRise_A	52871501	21373	0	0
CascadeLcToLcAonAboveFall_A	1601826	21373	0	0
CascadeLcToLcAonAboveRise_A	1601826	21373	0	0
CascadeLcToLcShadowedAboveFall_A	52871501	21373	0	0
CascadeLcToLcShadowedAboveRise_A	52871501	21373	0	0
CascadePorToAonAboveFall_A	1601826	7162	0	0
CascadeSysToSysAboveFall_A	52871501	21373	0	0
CascadeSysToSysAboveRise_A	52871501	21373	0	0
ScanRstToAonRise_A	1601826	221	0	0
StablePorToAonRise_A	1601826	8809	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11258312	21373	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11258312	21373	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11258312	21373	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11258312	21373	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12688937	21373	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12688937	21373	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11258312	21373	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11258312	21373	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11258312	21373	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11258312	21373	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871501	8809	0	0
T1	509140	109	0	0
T2	15850	2	0	0
T3	13006	2	0	0
T4	16734	2	0	0
T5	68847	16	0	0
T6	24433	8	0	0
T7	24886	2	0	0
T8	18689	2	0	0
T9	21784	2	0	0
T10	7485	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871501	8809	0	0
T1	509140	109	0	0
T2	15850	2	0	0
T3	13006	2	0	0
T4	16734	2	0	0
T5	68847	16	0	0
T6	24433	8	0	0
T7	24886	2	0	0
T8	18689	2	0	0
T9	21784	2	0	0
T10	7485	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50755042	8809	0	0
T1	488752	109	0	0
T2	15216	2	0	0
T3	12486	2	0	0
T4	16065	2	0	0
T5	66096	16	0	0
T6	23455	8	0	0
T7	23886	2	0	0
T8	17948	2	0	0
T9	20912	2	0	0
T10	7186	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50755042	8809	0	0
T1	488752	109	0	0
T2	15216	2	0	0
T3	12486	2	0	0
T4	16065	2	0	0
T5	66096	16	0	0
T6	23455	8	0	0
T7	23886	2	0	0
T8	17948	2	0	0
T9	20912	2	0	0
T10	7186	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378534	8809	0	0
T1	244355	109	0	0
T2	7607	2	0	0
T3	6242	2	0	0
T4	8032	2	0	0
T5	33044	16	0	0
T6	11726	8	0	0
T7	11942	2	0	0
T8	8973	2	0	0
T9	10455	2	0	0
T10	3591	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378534	8809	0	0
T1	244355	109	0	0
T2	7607	2	0	0
T3	6242	2	0	0
T4	8032	2	0	0
T5	33044	16	0	0
T6	11726	8	0	0
T7	11942	2	0	0
T8	8973	2	0	0
T9	10455	2	0	0
T10	3591	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	8809	0	0
T1	122193	109	0	0
T2	3804	2	0	0
T3	3120	2	0	0
T4	4016	2	0	0
T5	16524	16	0	0
T6	5862	8	0	0
T7	5972	2	0	0
T8	4486	2	0	0
T9	5228	2	0	0
T10	1795	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	8809	0	0
T1	122193	109	0	0
T2	3804	2	0	0
T3	3120	2	0	0
T4	4016	2	0	0
T5	16524	16	0	0
T6	5862	8	0	0
T7	5972	2	0	0
T8	4486	2	0	0
T9	5228	2	0	0
T10	1795	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378131	8809	0	0
T1	244374	109	0	0
T2	7608	2	0	0
T3	6242	2	0	0
T4	8031	2	0	0
T5	33041	16	0	0
T6	11726	8	0	0
T7	11946	2	0	0
T8	8970	2	0	0
T9	10456	2	0	0
T10	3592	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378131	8809	0	0
T1	244374	109	0	0
T2	7608	2	0	0
T3	6242	2	0	0
T4	8031	2	0	0
T5	33041	16	0	0
T6	11726	8	0	0
T7	11946	2	0	0
T8	8970	2	0	0
T9	10456	2	0	0
T10	3592	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871501	21373	0	0
T1	509140	277	0	0
T2	15850	2	0	0
T3	13006	2	0	0
T4	16734	2	0	0
T5	68847	43	0	0
T6	24433	8	0	0
T7	24886	6	0	0
T8	18689	6	0	0
T9	21784	2	0	0
T10	7485	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871501	21373	0	0
T1	509140	277	0	0
T2	15850	2	0	0
T3	13006	2	0	0
T4	16734	2	0	0
T5	68847	43	0	0
T6	24433	8	0	0
T7	24886	6	0	0
T8	18689	6	0	0
T9	21784	2	0	0
T10	7485	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601826	21373	0	0
T1	15575	277	0	0
T2	474	2	0	0
T3	390	2	0	0
T4	500	2	0	0
T5	2129	43	0	0
T6	734	8	0	0
T7	745	6	0	0
T8	560	6	0	0
T9	652	2	0	0
T10	223	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601826	21373	0	0
T1	15575	277	0	0
T2	474	2	0	0
T3	390	2	0	0
T4	500	2	0	0
T5	2129	43	0	0
T6	734	8	0	0
T7	745	6	0	0
T8	560	6	0	0
T9	652	2	0	0
T10	223	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871501	21373	0	0
T1	509140	277	0	0
T2	15850	2	0	0
T3	13006	2	0	0
T4	16734	2	0	0
T5	68847	43	0	0
T6	24433	8	0	0
T7	24886	6	0	0
T8	18689	6	0	0
T9	21784	2	0	0
T10	7485	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871501	21373	0	0
T1	509140	277	0	0
T2	15850	2	0	0
T3	13006	2	0	0
T4	16734	2	0	0
T5	68847	43	0	0
T6	24433	8	0	0
T7	24886	6	0	0
T8	18689	6	0	0
T9	21784	2	0	0
T10	7485	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601826	7162	0	0
T1	15575	61	0	0
T2	474	13	0	0
T3	390	9	0	0
T4	500	11	0	0
T5	2129	5	0	0
T6	734	8	0	0
T7	745	1	0	0
T8	560	1	0	0
T9	652	21	0	0
T10	223	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871501	21373	0	0
T1	509140	277	0	0
T2	15850	2	0	0
T3	13006	2	0	0
T4	16734	2	0	0
T5	68847	43	0	0
T6	24433	8	0	0
T7	24886	6	0	0
T8	18689	6	0	0
T9	21784	2	0	0
T10	7485	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871501	21373	0	0
T1	509140	277	0	0
T2	15850	2	0	0
T3	13006	2	0	0
T4	16734	2	0	0
T5	68847	43	0	0
T6	24433	8	0	0
T7	24886	6	0	0
T8	18689	6	0	0
T9	21784	2	0	0
T10	7485	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601826	221	0	0
T1	15575	8	0	0
T2	474	0	0	0
T3	390	0	0	0
T4	500	0	0	0
T5	2129	2	0	0
T6	734	0	0	0
T7	745	0	0	0
T8	560	1	0	0
T9	652	0	0	0
T10	223	0	0	0
T12	0	1	0	0
T51	0	3	0	0
T92	0	1	0	0
T94	0	4	0	0
T105	0	1	0	0
T106	0	3	0	0
T138	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601826	8809	0	0
T1	15575	109	0	0
T2	474	2	0	0
T3	390	2	0	0
T4	500	2	0	0
T5	2129	16	0	0
T6	734	8	0	0
T7	745	2	0	0
T8	560	2	0	0
T9	652	2	0	0
T10	223	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11258312	21373	0	0
T1	98905	277	0	0
T2	3665	2	0	0
T3	3054	2	0	0
T4	3925	2	0	0
T5	12751	43	0	0
T6	5509	8	0	0
T7	5680	6	0	0
T8	4291	6	0	0
T9	5184	2	0	0
T10	1753	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11258312	21373	0	0
T1	98905	277	0	0
T2	3665	2	0	0
T3	3054	2	0	0
T4	3925	2	0	0
T5	12751	43	0	0
T6	5509	8	0	0
T7	5680	6	0	0
T8	4291	6	0	0
T9	5184	2	0	0
T10	1753	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11258312	21373	0	0
T1	98905	277	0	0
T2	3665	2	0	0
T3	3054	2	0	0
T4	3925	2	0	0
T5	12751	43	0	0
T6	5509	8	0	0
T7	5680	6	0	0
T8	4291	6	0	0
T9	5184	2	0	0
T10	1753	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11258312	21373	0	0
T1	98905	277	0	0
T2	3665	2	0	0
T3	3054	2	0	0
T4	3925	2	0	0
T5	12751	43	0	0
T6	5509	8	0	0
T7	5680	6	0	0
T8	4291	6	0	0
T9	5184	2	0	0
T10	1753	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	21373	0	0
T1	122193	277	0	0
T2	3804	2	0	0
T3	3120	2	0	0
T4	4016	2	0	0
T5	16524	43	0	0
T6	5862	8	0	0
T7	5972	6	0	0
T8	4486	6	0	0
T9	5228	2	0	0
T10	1795	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	21373	0	0
T1	122193	277	0	0
T2	3804	2	0	0
T3	3120	2	0	0
T4	4016	2	0	0
T5	16524	43	0	0
T6	5862	8	0	0
T7	5972	6	0	0
T8	4486	6	0	0
T9	5228	2	0	0
T10	1795	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11258312	21373	0	0
T1	98905	277	0	0
T2	3665	2	0	0
T3	3054	2	0	0
T4	3925	2	0	0
T5	12751	43	0	0
T6	5509	8	0	0
T7	5680	6	0	0
T8	4291	6	0	0
T9	5184	2	0	0
T10	1753	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11258312	21373	0	0
T1	98905	277	0	0
T2	3665	2	0	0
T3	3054	2	0	0
T4	3925	2	0	0
T5	12751	43	0	0
T6	5509	8	0	0
T7	5680	6	0	0
T8	4291	6	0	0
T9	5184	2	0	0
T10	1753	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11258312	21373	0	0
T1	98905	277	0	0
T2	3665	2	0	0
T3	3054	2	0	0
T4	3925	2	0	0
T5	12751	43	0	0
T6	5509	8	0	0
T7	5680	6	0	0
T8	4291	6	0	0
T9	5184	2	0	0
T10	1753	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11258312	21373	0	0
T1	98905	277	0	0
T2	3665	2	0	0
T3	3054	2	0	0
T4	3925	2	0	0
T5	12751	43	0	0
T6	5509	8	0	0
T7	5680	6	0	0
T8	4291	6	0	0
T9	5184	2	0	0
T10	1753	1	0	0