Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T21
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T92
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T92
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T77
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T92
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12688937	13435	0	0
gen_assertions[0].RstEnOn_A	12688937	1070	0	0
gen_assertions[0].RstNOff_A	12688937	13435	0	0
gen_assertions[0].RstNOn_A	12688937	1070	0	0
gen_assertions[1].RstEnOff_A	50755042	12273	0	0
gen_assertions[1].RstEnOn_A	50755042	1040	0	0
gen_assertions[1].RstNOff_A	50755042	12273	0	0
gen_assertions[1].RstNOn_A	50755042	1040	0	0
gen_assertions[2].RstEnOff_A	25378534	12298	0	0
gen_assertions[2].RstEnOn_A	25378534	995	0	0
gen_assertions[2].RstNOff_A	25378534	12298	0	0
gen_assertions[2].RstNOn_A	25378534	995	0	0
gen_assertions[3].RstEnOff_A	25378131	12358	0	0
gen_assertions[3].RstEnOn_A	25378131	1053	0	0
gen_assertions[3].RstNOff_A	25378131	12358	0	0
gen_assertions[3].RstNOn_A	25378131	1053	0	0
gen_assertions[4].RstEnOff_A	1601826	21201	0	0
gen_assertions[4].RstEnOn_A	1601826	1116	0	0
gen_assertions[4].RstNOff_A	1601826	21201	0	0
gen_assertions[4].RstNOn_A	1601826	1116	0	0
gen_assertions[5].RstEnOff_A	12688937	13693	0	0
gen_assertions[5].RstEnOn_A	12688937	1156	0	0
gen_assertions[5].RstNOff_A	12688937	13693	0	0
gen_assertions[5].RstNOn_A	12688937	1156	0	0
gen_assertions[6].RstEnOff_A	12688937	13727	0	0
gen_assertions[6].RstEnOn_A	12688937	1198	0	0
gen_assertions[6].RstNOff_A	12688937	13727	0	0
gen_assertions[6].RstNOn_A	12688937	1198	0	0
gen_assertions[7].RstEnOff_A	12688937	13766	0	0
gen_assertions[7].RstEnOn_A	12688937	1241	0	0
gen_assertions[7].RstNOff_A	12688937	13766	0	0
gen_assertions[7].RstNOn_A	12688937	1241	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	13435	0	0
T1	122193	192	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	27	0	0
T6	5862	0	0	0
T7	5972	5	0	0
T8	4486	4	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	3	0	0
T12	0	39	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	19	0	0
T22	0	47	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	1070	0	0
T1	122193	24	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	0	0	0
T6	5862	0	0	0
T7	5972	1	0	0
T8	4486	0	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	3	0	0
T21	0	12	0	0
T70	0	4	0	0
T71	0	7	0	0
T77	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	22	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	13435	0	0
T1	122193	192	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	27	0	0
T6	5862	0	0	0
T7	5972	5	0	0
T8	4486	4	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	3	0	0
T12	0	39	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	19	0	0
T22	0	47	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	1070	0	0
T1	122193	24	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	0	0	0
T6	5862	0	0	0
T7	5972	1	0	0
T8	4486	0	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	3	0	0
T21	0	12	0	0
T70	0	4	0	0
T71	0	7	0	0
T77	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	22	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50755042	12273	0	0
T1	488752	179	0	0
T2	15216	0	0	0
T3	12486	0	0	0
T4	16065	0	0	0
T5	66096	23	0	0
T6	23455	0	0	0
T7	23886	4	0	0
T8	17948	4	0	0
T9	20912	0	0	0
T10	7186	0	0	0
T11	0	5	0	0
T12	0	36	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	15	0	0
T22	0	44	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50755042	1040	0	0
T1	488752	29	0	0
T2	15216	0	0	0
T3	12486	0	0	0
T4	16065	0	0	0
T5	66096	0	0	0
T6	23455	0	0	0
T7	23886	0	0	0
T8	17948	0	0	0
T9	20912	0	0	0
T10	7186	0	0	0
T11	0	5	0	0
T21	0	6	0	0
T51	0	12	0	0
T52	0	8	0	0
T70	0	6	0	0
T71	0	7	0	0
T92	0	2	0	0
T94	0	20	0	0
T95	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50755042	12273	0	0
T1	488752	179	0	0
T2	15216	0	0	0
T3	12486	0	0	0
T4	16065	0	0	0
T5	66096	23	0	0
T6	23455	0	0	0
T7	23886	4	0	0
T8	17948	4	0	0
T9	20912	0	0	0
T10	7186	0	0	0
T11	0	5	0	0
T12	0	36	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	15	0	0
T22	0	44	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50755042	1040	0	0
T1	488752	29	0	0
T2	15216	0	0	0
T3	12486	0	0	0
T4	16065	0	0	0
T5	66096	0	0	0
T6	23455	0	0	0
T7	23886	0	0	0
T8	17948	0	0	0
T9	20912	0	0	0
T10	7186	0	0	0
T11	0	5	0	0
T21	0	6	0	0
T51	0	12	0	0
T52	0	8	0	0
T70	0	6	0	0
T71	0	7	0	0
T92	0	2	0	0
T94	0	20	0	0
T95	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378534	12298	0	0
T1	244355	178	0	0
T2	7607	0	0	0
T3	6242	0	0	0
T4	8032	0	0	0
T5	33044	23	0	0
T6	11726	0	0	0
T7	11942	5	0	0
T8	8973	4	0	0
T9	10455	0	0	0
T10	3591	0	0	0
T11	0	3	0	0
T12	0	36	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	15	0	0
T22	0	44	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378534	995	0	0
T1	244355	27	0	0
T2	7607	0	0	0
T3	6242	0	0	0
T4	8032	0	0	0
T5	33044	0	0	0
T6	11726	0	0	0
T7	11942	1	0	0
T8	8973	0	0	0
T9	10455	0	0	0
T10	3591	0	0	0
T11	0	3	0	0
T21	0	1	0	0
T51	0	11	0	0
T52	0	9	0	0
T70	0	6	0	0
T71	0	10	0	0
T92	0	3	0	0
T94	0	22	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378534	12298	0	0
T1	244355	178	0	0
T2	7607	0	0	0
T3	6242	0	0	0
T4	8032	0	0	0
T5	33044	23	0	0
T6	11726	0	0	0
T7	11942	5	0	0
T8	8973	4	0	0
T9	10455	0	0	0
T10	3591	0	0	0
T11	0	3	0	0
T12	0	36	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	15	0	0
T22	0	44	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378534	995	0	0
T1	244355	27	0	0
T2	7607	0	0	0
T3	6242	0	0	0
T4	8032	0	0	0
T5	33044	0	0	0
T6	11726	0	0	0
T7	11942	1	0	0
T8	8973	0	0	0
T9	10455	0	0	0
T10	3591	0	0	0
T11	0	3	0	0
T21	0	1	0	0
T51	0	11	0	0
T52	0	9	0	0
T70	0	6	0	0
T71	0	10	0	0
T92	0	3	0	0
T94	0	22	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378131	12358	0	0
T1	244374	180	0	0
T2	7608	0	0	0
T3	6242	0	0	0
T4	8031	0	0	0
T5	33041	23	0	0
T6	11726	0	0	0
T7	11946	5	0	0
T8	8970	4	0	0
T9	10456	0	0	0
T10	3592	0	0	0
T11	0	8	0	0
T12	0	36	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	15	0	0
T22	0	44	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378131	1053	0	0
T1	244374	29	0	0
T2	7608	0	0	0
T3	6242	0	0	0
T4	8031	0	0	0
T5	33041	0	0	0
T6	11726	0	0	0
T7	11946	1	0	0
T8	8970	0	0	0
T9	10456	0	0	0
T10	3592	0	0	0
T11	0	8	0	0
T51	0	15	0	0
T52	0	8	0	0
T70	0	8	0	0
T71	0	10	0	0
T92	0	3	0	0
T94	0	24	0	0
T96	0	26	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378131	12358	0	0
T1	244374	180	0	0
T2	7608	0	0	0
T3	6242	0	0	0
T4	8031	0	0	0
T5	33041	23	0	0
T6	11726	0	0	0
T7	11946	5	0	0
T8	8970	4	0	0
T9	10456	0	0	0
T10	3592	0	0	0
T11	0	8	0	0
T12	0	36	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	15	0	0
T22	0	44	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25378131	1053	0	0
T1	244374	29	0	0
T2	7608	0	0	0
T3	6242	0	0	0
T4	8031	0	0	0
T5	33041	0	0	0
T6	11726	0	0	0
T7	11946	1	0	0
T8	8970	0	0	0
T9	10456	0	0	0
T10	3592	0	0	0
T11	0	8	0	0
T51	0	15	0	0
T52	0	8	0	0
T70	0	8	0	0
T71	0	10	0	0
T92	0	3	0	0
T94	0	24	0	0
T96	0	26	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601826	21201	0	0
T1	15575	296	0	0
T2	474	2	0	0
T3	390	2	0	0
T4	500	2	0	0
T5	2129	43	0	0
T6	734	3	0	0
T7	745	6	0	0
T8	560	6	0	0
T9	652	2	0	0
T10	223	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601826	1116	0	0
T1	15575	27	0	0
T2	474	0	0	0
T3	390	0	0	0
T4	500	0	0	0
T5	2129	0	0	0
T6	734	0	0	0
T7	745	0	0	0
T8	560	0	0	0
T9	652	0	0	0
T10	223	0	0	0
T11	0	9	0	0
T51	0	13	0	0
T52	0	10	0	0
T70	0	8	0	0
T71	0	12	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	21	0	0
T96	0	20	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601826	21201	0	0
T1	15575	296	0	0
T2	474	2	0	0
T3	390	2	0	0
T4	500	2	0	0
T5	2129	43	0	0
T6	734	3	0	0
T7	745	6	0	0
T8	560	6	0	0
T9	652	2	0	0
T10	223	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601826	1116	0	0
T1	15575	27	0	0
T2	474	0	0	0
T3	390	0	0	0
T4	500	0	0	0
T5	2129	0	0	0
T6	734	0	0	0
T7	745	0	0	0
T8	560	0	0	0
T9	652	0	0	0
T10	223	0	0	0
T11	0	9	0	0
T51	0	13	0	0
T52	0	10	0	0
T70	0	8	0	0
T71	0	12	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	21	0	0
T96	0	20	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	13693	0	0
T1	122193	194	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	27	0	0
T6	5862	0	0	0
T7	5972	4	0	0
T8	4486	4	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	10	0	0
T12	0	39	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	19	0	0
T22	0	47	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	1156	0	0
T1	122193	27	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	0	0	0
T6	5862	0	0	0
T7	5972	0	0	0
T8	4486	0	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	10	0	0
T50	0	1	0	0
T51	0	11	0	0
T52	0	10	0	0
T70	0	9	0	0
T71	0	14	0	0
T92	0	2	0	0
T94	0	21	0	0
T96	0	25	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	13693	0	0
T1	122193	194	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	27	0	0
T6	5862	0	0	0
T7	5972	4	0	0
T8	4486	4	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	10	0	0
T12	0	39	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	19	0	0
T22	0	47	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	1156	0	0
T1	122193	27	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	0	0	0
T6	5862	0	0	0
T7	5972	0	0	0
T8	4486	0	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	10	0	0
T50	0	1	0	0
T51	0	11	0	0
T52	0	10	0	0
T70	0	9	0	0
T71	0	14	0	0
T92	0	2	0	0
T94	0	21	0	0
T96	0	25	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	13727	0	0
T1	122193	191	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	27	0	0
T6	5862	0	0	0
T7	5972	4	0	0
T8	4486	4	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	10	0	0
T12	0	39	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	19	0	0
T22	0	47	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	1198	0	0
T1	122193	23	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	0	0	0
T6	5862	0	0	0
T7	5972	0	0	0
T8	4486	0	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	10	0	0
T51	0	13	0	0
T52	0	13	0	0
T70	0	11	0	0
T71	0	16	0	0
T77	0	1	0	0
T92	0	1	0	0
T94	0	17	0	0
T96	0	23	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	13727	0	0
T1	122193	191	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	27	0	0
T6	5862	0	0	0
T7	5972	4	0	0
T8	4486	4	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	10	0	0
T12	0	39	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	19	0	0
T22	0	47	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	1198	0	0
T1	122193	23	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	0	0	0
T6	5862	0	0	0
T7	5972	0	0	0
T8	4486	0	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	10	0	0
T51	0	13	0	0
T52	0	13	0	0
T70	0	11	0	0
T71	0	16	0	0
T77	0	1	0	0
T92	0	1	0	0
T94	0	17	0	0
T96	0	23	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	13766	0	0
T1	122193	191	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	27	0	0
T6	5862	0	0	0
T7	5972	4	0	0
T8	4486	4	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	11	0	0
T12	0	39	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	19	0	0
T22	0	47	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	1241	0	0
T1	122193	24	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	0	0	0
T6	5862	0	0	0
T7	5972	0	0	0
T8	4486	0	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	11	0	0
T51	0	14	0	0
T52	0	15	0	0
T70	0	10	0	0
T71	0	12	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	23	0	0
T96	0	22	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	13766	0	0
T1	122193	191	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	27	0	0
T6	5862	0	0	0
T7	5972	4	0	0
T8	4486	4	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	11	0	0
T12	0	39	0	0
T13	0	4	0	0
T20	0	4	0	0
T21	0	19	0	0
T22	0	47	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12688937	1241	0	0
T1	122193	24	0	0
T2	3804	0	0	0
T3	3120	0	0	0
T4	4016	0	0	0
T5	16524	0	0	0
T6	5862	0	0	0
T7	5972	0	0	0
T8	4486	0	0	0
T9	5228	0	0	0
T10	1795	0	0	0
T11	0	11	0	0
T51	0	14	0	0
T52	0	15	0	0
T70	0	10	0	0
T71	0	12	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	23	0	0
T96	0	22	0	0