Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12122198	7445	0	0
alert_regwen_rd_A	12122198	4493	0	0
cpu_regwen_rd_A	12122198	4330	0	0
sw_rst_ctrl_n_0_rd_A	12122198	7216	0	0
sw_rst_ctrl_n_1_rd_A	12122198	7119	0	0
sw_rst_ctrl_n_2_rd_A	12122198	6989	0	0
sw_rst_ctrl_n_3_rd_A	12122198	7188	0	0
sw_rst_ctrl_n_4_rd_A	12122198	7254	0	0
sw_rst_ctrl_n_5_rd_A	12122198	7151	0	0
sw_rst_ctrl_n_6_rd_A	12122198	7046	0	0
sw_rst_ctrl_n_7_rd_A	12122198	7078	0	0
sw_rst_regwen_0_rd_A	12122198	4938	0	0
sw_rst_regwen_1_rd_A	12122198	4945	0	0
sw_rst_regwen_2_rd_A	12122198	4830	0	0
sw_rst_regwen_3_rd_A	12122198	4943	0	0
sw_rst_regwen_4_rd_A	12122198	4780	0	0
sw_rst_regwen_5_rd_A	12122198	4905	0	0
sw_rst_regwen_6_rd_A	12122198	4783	0	0
sw_rst_regwen_7_rd_A	12122198	5004	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	7445	0	0
T73	4402	18	0	0
T78	9741	334	0	0
T79	4641	179	0	0
T80	3925	467	0	0
T81	19102	3	0	0
T86	9562	1	0	0
T97	16805	2	0	0
T98	6206	155	0	0
T99	3048	13	0	0
T100	2720	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	4493	0	0
T12	38418	52	0	0
T13	3341	0	0	0
T20	2099	0	0	0
T21	2780	0	0	0
T22	16909	0	0	0
T23	3827	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T42	0	38	0	0
T58	5274	0	0	0
T85	1610	0	0	0
T92	0	62	0	0
T94	0	108	0	0
T106	0	68	0	0
T107	0	64	0	0
T111	0	33	0	0
T133	0	55	0	0
T134	0	61	0	0
T135	0	247	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	4330	0	0
T12	38418	75	0	0
T13	3341	0	0	0
T20	2099	0	0	0
T21	2780	0	0	0
T22	16909	0	0	0
T23	3827	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T42	0	25	0	0
T58	5274	0	0	0
T85	1610	0	0	0
T92	0	58	0	0
T94	0	134	0	0
T106	0	42	0	0
T107	0	83	0	0
T111	0	38	0	0
T133	0	33	0	0
T134	0	41	0	0
T135	0	308	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	7216	0	0
T7	5680	24	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	188	0	0
T12	38418	41	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T77	0	23	0	0
T84	1656	0	0	0
T92	0	83	0	0
T93	0	11	0	0
T94	0	467	0	0
T106	0	61	0	0
T107	0	67	0	0
T136	0	3	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	7119	0	0
T7	5680	19	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	171	0	0
T12	38418	49	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T77	0	3	0	0
T84	1656	0	0	0
T92	0	98	0	0
T93	0	6	0	0
T94	0	430	0	0
T106	0	52	0	0
T107	0	69	0	0
T136	0	3	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	6989	0	0
T7	5680	5	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	157	0	0
T12	38418	80	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T62	0	10	0	0
T77	0	16	0	0
T84	1656	0	0	0
T92	0	88	0	0
T93	0	11	0	0
T94	0	428	0	0
T106	0	55	0	0
T107	0	102	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	7188	0	0
T7	5680	9	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	136	0	0
T12	38418	61	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T77	0	9	0	0
T84	1656	0	0	0
T92	0	67	0	0
T93	0	11	0	0
T94	0	400	0	0
T106	0	55	0	0
T107	0	70	0	0
T136	0	4	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	7254	0	0
T7	5680	23	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	152	0	0
T12	38418	73	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T77	0	5	0	0
T84	1656	0	0	0
T92	0	92	0	0
T93	0	8	0	0
T94	0	470	0	0
T106	0	75	0	0
T107	0	79	0	0
T136	0	8	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	7151	0	0
T7	5680	26	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	158	0	0
T12	38418	39	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T77	0	9	0	0
T84	1656	0	0	0
T92	0	65	0	0
T93	0	10	0	0
T94	0	421	0	0
T106	0	73	0	0
T107	0	84	0	0
T136	0	7	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	7046	0	0
T7	5680	14	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	148	0	0
T12	38418	46	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T77	0	8	0	0
T84	1656	0	0	0
T92	0	73	0	0
T93	0	6	0	0
T94	0	342	0	0
T106	0	66	0	0
T107	0	60	0	0
T136	0	2	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	7078	0	0
T7	5680	16	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	174	0	0
T12	38418	39	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T62	0	3	0	0
T77	0	16	0	0
T84	1656	0	0	0
T92	0	93	0	0
T93	0	9	0	0
T94	0	419	0	0
T106	0	54	0	0
T107	0	67	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	4938	0	0
T7	5680	4	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	23	0	0
T12	38418	55	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T42	0	28	0	0
T77	0	13	0	0
T84	1656	0	0	0
T92	0	57	0	0
T93	0	4	0	0
T94	0	109	0	0
T106	0	69	0	0
T107	0	56	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	4945	0	0
T7	5680	7	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	23	0	0
T12	38418	56	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T62	0	8	0	0
T77	0	9	0	0
T84	1656	0	0	0
T92	0	53	0	0
T93	0	5	0	0
T94	0	103	0	0
T106	0	72	0	0
T107	0	61	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	4830	0	0
T7	5680	7	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	22	0	0
T12	38418	46	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T42	0	20	0	0
T77	0	8	0	0
T84	1656	0	0	0
T92	0	49	0	0
T93	0	8	0	0
T94	0	120	0	0
T106	0	51	0	0
T107	0	75	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	4943	0	0
T7	5680	5	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	35	0	0
T12	38418	74	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T62	0	2	0	0
T77	0	5	0	0
T84	1656	0	0	0
T92	0	42	0	0
T93	0	7	0	0
T94	0	107	0	0
T106	0	72	0	0
T107	0	83	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	4780	0	0
T7	5680	13	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	34	0	0
T12	38418	62	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T62	0	1	0	0
T77	0	4	0	0
T84	1656	0	0	0
T92	0	64	0	0
T93	0	5	0	0
T94	0	139	0	0
T106	0	63	0	0
T107	0	85	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	4905	0	0
T7	5680	2	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	25	0	0
T12	38418	73	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T62	0	7	0	0
T77	0	9	0	0
T84	1656	0	0	0
T92	0	46	0	0
T93	0	7	0	0
T94	0	114	0	0
T106	0	72	0	0
T107	0	75	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	4783	0	0
T7	5680	7	0	0
T8	4291	0	0	0
T9	5184	0	0	0
T10	1753	0	0	0
T11	10646	42	0	0
T12	38418	53	0	0
T13	3341	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T62	0	10	0	0
T77	0	1	0	0
T84	1656	0	0	0
T92	0	36	0	0
T93	0	7	0	0
T94	0	108	0	0
T106	0	49	0	0
T107	0	42	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12122198	5004	0	0
T11	10646	30	0	0
T12	38418	46	0	0
T13	3341	0	0	0
T20	2099	0	0	0
T21	2780	0	0	0
T24	5091	0	0	0
T25	5490	0	0	0
T42	0	43	0	0
T58	5274	0	0	0
T77	0	3	0	0
T84	1656	0	0	0
T85	1610	0	0	0
T92	0	74	0	0
T93	0	7	0	0
T94	0	116	0	0
T106	0	58	0	0
T107	0	62	0	0
T137	0	21	0	0