Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	583101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

347619

1

T1

140

T2

2

T3

81

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	496185	1			T1	186		T3	99		T4	1500
values[0x0]	216774	1			T1	102		T2	7		T3	62
values[0x1]	217761	1			T1	91		T2	8		T3	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	489330	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

441390

1

T1

175

T2

3

T3

104

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3410	1			T6	32		T11	1		T31	9
valid_sources[0x01]	3127	1			T6	6		T11	1		T31	7
valid_sources[0x02]	3350	1			T11	1		T12	1		T31	21
valid_sources[0x03]	3123	1			T11	1		T31	16		T25	6
valid_sources[0x04]	5183	1			T7	4		T12	4		T31	10
valid_sources[0x05]	3567	1			T6	16		T12	2		T31	13
valid_sources[0x06]	3054	1			T6	3		T7	2		T10	1
valid_sources[0x07]	3626	1			T6	13		T7	3		T31	22
valid_sources[0x08]	3140	1			T6	10		T7	3		T11	1
valid_sources[0x09]	2993	1			T6	6		T31	17		T55	15
valid_sources[0x0a]	3107	1			T6	30		T7	1		T31	15
valid_sources[0x0b]	3114	1			T11	1		T31	29		T25	11
valid_sources[0x0c]	3413	1			T6	3		T11	1		T31	11
valid_sources[0x0d]	3975	1			T6	2		T31	9		T25	9
valid_sources[0x0e]	4169	1			T6	16		T7	1		T31	10
valid_sources[0x0f]	4388	1			T6	6		T7	1		T11	1
valid_sources[0x10]	3315	1			T6	10		T11	2		T31	10
valid_sources[0x11]	2915	1			T2	1		T6	7		T11	1
valid_sources[0x12]	3186	1			T6	15		T7	1		T10	1
valid_sources[0x13]	3036	1			T6	22		T7	3		T11	2
valid_sources[0x14]	3473	1			T6	10		T10	1		T11	1
valid_sources[0x15]	3156	1			T6	16		T7	1		T10	1
valid_sources[0x16]	5509	1			T2	3		T6	12		T7	4
valid_sources[0x17]	2876	1			T6	10		T31	6		T25	11
valid_sources[0x18]	5030	1			T6	1		T7	1		T11	2
valid_sources[0x19]	2921	1			T6	3		T7	1		T12	3
valid_sources[0x1a]	4018	1			T7	1		T12	3		T31	11
valid_sources[0x1b]	2959	1			T6	2		T11	1		T12	1
valid_sources[0x1c]	3423	1			T6	7		T7	1		T10	1
valid_sources[0x1d]	4701	1			T6	4		T7	1		T11	2
valid_sources[0x1e]	3106	1			T6	3		T7	1		T10	1
valid_sources[0x1f]	3390	1			T6	12		T11	1		T31	24
valid_sources[0x20]	4629	1			T6	13		T7	1		T10	1
valid_sources[0x21]	3306	1			T6	7		T10	2		T11	1
valid_sources[0x22]	3636	1			T6	2		T7	1		T11	1
valid_sources[0x23]	3298	1			T6	18		T11	1		T12	3
valid_sources[0x24]	3538	1			T6	4		T7	2		T11	1
valid_sources[0x25]	4138	1			T6	1		T7	1		T11	4
valid_sources[0x26]	4426	1			T6	1		T12	4		T31	10
valid_sources[0x27]	3488	1			T6	6		T7	1		T31	12
valid_sources[0x28]	2964	1			T6	20		T11	1		T31	13
valid_sources[0x29]	3734	1			T2	1		T6	15		T7	1
valid_sources[0x2a]	3504	1			T6	8		T7	1		T11	1
valid_sources[0x2b]	3202	1			T6	5		T7	1		T11	1
valid_sources[0x2c]	2763	1			T11	1		T31	9		T25	12
valid_sources[0x2d]	3815	1			T2	1		T6	23		T12	2
valid_sources[0x2e]	3334	1			T6	11		T7	3		T12	3
valid_sources[0x2f]	3227	1			T6	1		T7	1		T11	1
valid_sources[0x30]	4755	1			T6	30		T7	3		T11	2
valid_sources[0x31]	3004	1			T6	5		T11	2		T31	12
valid_sources[0x32]	3367	1			T6	3		T11	1		T31	5
valid_sources[0x33]	3392	1			T6	4		T7	2		T12	2
valid_sources[0x34]	3049	1			T9	11		T11	1		T31	6
valid_sources[0x35]	3772	1			T6	14		T7	1		T11	1
valid_sources[0x36]	4206	1			T7	1		T11	1		T31	10
valid_sources[0x37]	4826	1			T6	16		T7	1		T10	1
valid_sources[0x38]	3395	1			T6	14		T7	2		T31	4
valid_sources[0x39]	3651	1			T9	1		T11	2		T12	5
valid_sources[0x3a]	3758	1			T7	1		T31	15		T55	9
valid_sources[0x3b]	3660	1			T6	4		T7	1		T11	2
valid_sources[0x3c]	3187	1			T2	1		T6	1		T11	1
valid_sources[0x3d]	3374	1			T6	13		T7	2		T31	9
valid_sources[0x3e]	4519	1			T6	5		T11	1		T12	1
valid_sources[0x3f]	3097	1			T6	15		T7	3		T11	2
valid_sources[0x40]	2958	1			T6	8		T12	1		T31	13
valid_sources[0x41]	3014	1			T6	9		T31	9		T25	11
valid_sources[0x42]	3546	1			T6	1		T31	12		T25	14
valid_sources[0x43]	3459	1			T6	4		T11	3		T31	14
valid_sources[0x44]	2992	1			T6	8		T7	1		T31	7
valid_sources[0x45]	3096	1			T31	11		T25	9		T57	86
valid_sources[0x46]	3038	1			T6	1		T11	3		T12	1
valid_sources[0x47]	3354	1			T7	1		T12	1		T31	9
valid_sources[0x48]	3946	1			T6	6		T7	1		T11	1
valid_sources[0x49]	4141	1			T6	4		T7	4		T10	1
valid_sources[0x4a]	3527	1			T6	9		T12	2		T31	11
valid_sources[0x4b]	3832	1			T7	1		T10	1		T11	1
valid_sources[0x4c]	3391	1			T6	22		T7	1		T11	2
valid_sources[0x4d]	3567	1			T6	13		T31	10		T25	10
valid_sources[0x4e]	3252	1			T6	8		T9	1		T11	1
valid_sources[0x4f]	6782	1			T6	5		T7	1		T12	1
valid_sources[0x50]	3220	1			T6	24		T11	1		T12	2
valid_sources[0x51]	3035	1			T6	8		T7	1		T11	3
valid_sources[0x52]	3128	1			T6	2		T12	1		T31	12
valid_sources[0x53]	3911	1			T12	1		T31	16		T25	6
valid_sources[0x54]	2787	1			T6	20		T9	3		T11	1
valid_sources[0x55]	3770	1			T6	34		T31	6		T55	5
valid_sources[0x56]	3056	1			T6	7		T31	9		T25	9
valid_sources[0x57]	3146	1			T6	6		T7	1		T12	2
valid_sources[0x58]	3670	1			T6	4		T7	2		T11	4
valid_sources[0x59]	2876	1			T6	36		T7	2		T11	1
valid_sources[0x5a]	3082	1			T12	5		T31	19		T55	13
valid_sources[0x5b]	3848	1			T1	379		T6	31		T11	2
valid_sources[0x5c]	3335	1			T6	14		T40	9		T11	1
valid_sources[0x5d]	2882	1			T6	2		T31	15		T25	9
valid_sources[0x5e]	6323	1			T6	1		T12	2		T31	20
valid_sources[0x5f]	3593	1			T6	12		T11	1		T31	23
valid_sources[0x60]	4274	1			T6	15		T7	1		T11	1
valid_sources[0x61]	3058	1			T2	1		T6	6		T7	3
valid_sources[0x62]	2897	1			T6	10		T11	1		T31	14
valid_sources[0x63]	3538	1			T6	1		T11	2		T12	1
valid_sources[0x64]	3406	1			T6	22		T7	1		T11	2
valid_sources[0x65]	5928	1			T6	9		T11	1		T12	2
valid_sources[0x66]	3376	1			T6	1		T10	1		T11	1
valid_sources[0x67]	6826	1			T6	9		T11	3		T31	8
valid_sources[0x68]	4250	1			T6	4		T11	1		T31	26
valid_sources[0x69]	3290	1			T6	7		T11	1		T31	11
valid_sources[0x6a]	7047	1			T4	3200		T6	9		T10	1
valid_sources[0x6b]	3234	1			T6	8		T7	2		T10	1
valid_sources[0x6c]	3286	1			T6	3		T11	2		T31	16
valid_sources[0x6d]	3271	1			T6	28		T7	1		T31	11
valid_sources[0x6e]	3177	1			T6	21		T11	1		T31	13
valid_sources[0x6f]	3553	1			T6	11		T7	1		T12	1
valid_sources[0x70]	3100	1			T6	25		T10	1		T31	9
valid_sources[0x71]	4010	1			T6	19		T31	12		T25	10
valid_sources[0x72]	3217	1			T6	19		T7	2		T12	4
valid_sources[0x73]	3443	1			T6	10		T7	1		T11	1
valid_sources[0x74]	3456	1			T6	3		T7	1		T11	1
valid_sources[0x75]	3227	1			T6	11		T11	2		T31	11
valid_sources[0x76]	3007	1			T6	3		T7	6		T31	13
valid_sources[0x77]	3159	1			T6	4		T9	4		T10	1
valid_sources[0x78]	2991	1			T7	1		T31	16		T25	2
valid_sources[0x79]	3821	1			T6	17		T11	1		T31	16
valid_sources[0x7a]	3616	1			T7	3		T9	1		T11	2
valid_sources[0x7b]	7000	1			T6	13		T10	1		T11	1
valid_sources[0x7c]	3048	1			T7	5		T11	3		T12	2
valid_sources[0x7d]	3618	1			T6	4		T11	2		T31	7
valid_sources[0x7e]	2991	1			T6	3		T11	1		T31	11
valid_sources[0x7f]	3276	1			T6	6		T31	11		T55	1
valid_sources[0x80]	5287	1			T6	23		T10	2		T31	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

232245

1

T1

89

T3

47

T4

665

values[0x0]

all_enables

biggest_size

75370

1

T1

40

T2

1

T3

27

values[0x1]

all_enables

biggest_size

40004

1

T1

11

T2

1

T3

7