Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T6,T11,T12
1	0	Covered	T55,T25,T56

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	50811519	8498	0	0
CascadeEffAonToRstPorAboveRise_A	50811519	8498	0	0
CascadeEffAonToRstPorIoAboveFall_A	48777261	8498	0	0
CascadeEffAonToRstPorIoAboveRise_A	48777261	8498	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24389480	8498	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24389480	8498	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12194406	8498	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12194406	8498	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24389324	8498	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24389324	8498	0	0
CascadeLcToLcAboveFall_A	50811519	20916	0	0
CascadeLcToLcAboveRise_A	50811519	20916	0	0
CascadeLcToLcAonAboveFall_A	1539781	20916	0	0
CascadeLcToLcAonAboveRise_A	1539781	20916	0	0
CascadeLcToLcShadowedAboveFall_A	50811519	20916	0	0
CascadeLcToLcShadowedAboveRise_A	50811519	20916	0	0
CascadePorToAonAboveFall_A	1539781	6882	0	0
CascadeSysToSysAboveFall_A	50811519	20916	0	0
CascadeSysToSysAboveRise_A	50811519	20916	0	0
ScanRstToAonRise_A	1539781	211	0	0
StablePorToAonRise_A	1539781	8498	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10760655	20916	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10760655	20916	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10760655	20916	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10760655	20916	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12194406	20916	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12194406	20916	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10760655	20916	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10760655	20916	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10760655	20916	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10760655	20916	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50811519	8498	0	0
T1	12182	2	0	0
T2	7869	1	0	0
T3	16085	2	0	0
T4	189305	27	0	0
T5	24721	8	0	0
T6	70827	13	0	0
T7	14918	2	0	0
T8	12728	1	0	0
T9	8096	1	0	0
T10	6056	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50811519	8498	0	0
T1	12182	2	0	0
T2	7869	1	0	0
T3	16085	2	0	0
T4	189305	27	0	0
T5	24721	8	0	0
T6	70827	13	0	0
T7	14918	2	0	0
T8	12728	1	0	0
T9	8096	1	0	0
T10	6056	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48777261	8498	0	0
T1	11696	2	0	0
T2	7554	1	0	0
T3	15441	2	0	0
T4	181725	27	0	0
T5	23739	8	0	0
T6	67982	13	0	0
T7	14316	2	0	0
T8	12217	1	0	0
T9	7772	1	0	0
T10	5813	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48777261	8498	0	0
T1	11696	2	0	0
T2	7554	1	0	0
T3	15441	2	0	0
T4	181725	27	0	0
T5	23739	8	0	0
T6	67982	13	0	0
T7	14316	2	0	0
T8	12217	1	0	0
T9	7772	1	0	0
T10	5813	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389480	8498	0	0
T1	5843	2	0	0
T2	3777	1	0	0
T3	7720	2	0	0
T4	90864	27	0	0
T5	11867	8	0	0
T6	33993	13	0	0
T7	7157	2	0	0
T8	6108	1	0	0
T9	3886	1	0	0
T10	2906	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389480	8498	0	0
T1	5843	2	0	0
T2	3777	1	0	0
T3	7720	2	0	0
T4	90864	27	0	0
T5	11867	8	0	0
T6	33993	13	0	0
T7	7157	2	0	0
T8	6108	1	0	0
T9	3886	1	0	0
T10	2906	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	8498	0	0
T1	2921	2	0	0
T2	1888	1	0	0
T3	3859	2	0	0
T4	45425	27	0	0
T5	5932	8	0	0
T6	16996	13	0	0
T7	3577	2	0	0
T8	3053	1	0	0
T9	1942	1	0	0
T10	1452	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	8498	0	0
T1	2921	2	0	0
T2	1888	1	0	0
T3	3859	2	0	0
T4	45425	27	0	0
T5	5932	8	0	0
T6	16996	13	0	0
T7	3577	2	0	0
T8	3053	1	0	0
T9	1942	1	0	0
T10	1452	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389324	8498	0	0
T1	5846	2	0	0
T2	3777	1	0	0
T3	7720	2	0	0
T4	90864	27	0	0
T5	11871	8	0	0
T6	34000	13	0	0
T7	7157	2	0	0
T8	6109	1	0	0
T9	3886	1	0	0
T10	2906	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389324	8498	0	0
T1	5846	2	0	0
T2	3777	1	0	0
T3	7720	2	0	0
T4	90864	27	0	0
T5	11871	8	0	0
T6	34000	13	0	0
T7	7157	2	0	0
T8	6109	1	0	0
T9	3886	1	0	0
T10	2906	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50811519	20916	0	0
T1	12182	6	0	0
T2	7869	1	0	0
T3	16085	6	0	0
T4	189305	102	0	0
T5	24721	8	0	0
T6	70827	45	0	0
T7	14918	6	0	0
T8	12728	7	0	0
T9	8096	1	0	0
T10	6056	3	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50811519	20916	0	0
T1	12182	6	0	0
T2	7869	1	0	0
T3	16085	6	0	0
T4	189305	102	0	0
T5	24721	8	0	0
T6	70827	45	0	0
T7	14918	6	0	0
T8	12728	7	0	0
T9	8096	1	0	0
T10	6056	3	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539781	20916	0	0
T1	364	6	0	0
T2	234	1	0	0
T3	481	6	0	0
T4	5693	102	0	0
T5	743	8	0	0
T6	2161	45	0	0
T7	447	6	0	0
T8	380	7	0	0
T9	242	1	0	0
T10	180	3	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539781	20916	0	0
T1	364	6	0	0
T2	234	1	0	0
T3	481	6	0	0
T4	5693	102	0	0
T5	743	8	0	0
T6	2161	45	0	0
T7	447	6	0	0
T8	380	7	0	0
T9	242	1	0	0
T10	180	3	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50811519	20916	0	0
T1	12182	6	0	0
T2	7869	1	0	0
T3	16085	6	0	0
T4	189305	102	0	0
T5	24721	8	0	0
T6	70827	45	0	0
T7	14918	6	0	0
T8	12728	7	0	0
T9	8096	1	0	0
T10	6056	3	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50811519	20916	0	0
T1	12182	6	0	0
T2	7869	1	0	0
T3	16085	6	0	0
T4	189305	102	0	0
T5	24721	8	0	0
T6	70827	45	0	0
T7	14918	6	0	0
T8	12728	7	0	0
T9	8096	1	0	0
T10	6056	3	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539781	6882	0	0
T1	364	1	0	0
T2	234	1	0	0
T3	481	1	0	0
T4	5693	27	0	0
T5	743	8	0	0
T6	2161	7	0	0
T7	447	1	0	0
T8	380	1	0	0
T9	242	1	0	0
T10	180	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50811519	20916	0	0
T1	12182	6	0	0
T2	7869	1	0	0
T3	16085	6	0	0
T4	189305	102	0	0
T5	24721	8	0	0
T6	70827	45	0	0
T7	14918	6	0	0
T8	12728	7	0	0
T9	8096	1	0	0
T10	6056	3	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50811519	20916	0	0
T1	12182	6	0	0
T2	7869	1	0	0
T3	16085	6	0	0
T4	189305	102	0	0
T5	24721	8	0	0
T6	70827	45	0	0
T7	14918	6	0	0
T8	12728	7	0	0
T9	8096	1	0	0
T10	6056	3	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539781	211	0	0
T11	410	1	0	0
T12	318	0	0	0
T13	439	0	0	0
T14	482	0	0	0
T24	573	0	0	0
T25	4031	3	0	0
T26	443	0	0	0
T31	3692	0	0	0
T41	215	0	0	0
T52	0	1	0	0
T55	1250	0	0	0
T56	0	1	0	0
T57	0	6	0	0
T64	0	1	0	0
T94	0	2	0	0
T96	0	3	0	0
T105	0	1	0	0
T108	0	7	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539781	8498	0	0
T1	364	2	0	0
T2	234	1	0	0
T3	481	2	0	0
T4	5693	27	0	0
T5	743	8	0	0
T6	2161	13	0	0
T7	447	2	0	0
T8	380	1	0	0
T9	242	1	0	0
T10	180	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10760655	20916	0	0
T1	2682	6	0	0
T2	1845	1	0	0
T3	3521	6	0	0
T4	42089	102	0	0
T5	5581	8	0	0
T6	12668	45	0	0
T7	3338	6	0	0
T8	2619	7	0	0
T9	1899	1	0	0
T10	1327	3	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10760655	20916	0	0
T1	2682	6	0	0
T2	1845	1	0	0
T3	3521	6	0	0
T4	42089	102	0	0
T5	5581	8	0	0
T6	12668	45	0	0
T7	3338	6	0	0
T8	2619	7	0	0
T9	1899	1	0	0
T10	1327	3	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10760655	20916	0	0
T1	2682	6	0	0
T2	1845	1	0	0
T3	3521	6	0	0
T4	42089	102	0	0
T5	5581	8	0	0
T6	12668	45	0	0
T7	3338	6	0	0
T8	2619	7	0	0
T9	1899	1	0	0
T10	1327	3	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10760655	20916	0	0
T1	2682	6	0	0
T2	1845	1	0	0
T3	3521	6	0	0
T4	42089	102	0	0
T5	5581	8	0	0
T6	12668	45	0	0
T7	3338	6	0	0
T8	2619	7	0	0
T9	1899	1	0	0
T10	1327	3	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	20916	0	0
T1	2921	6	0	0
T2	1888	1	0	0
T3	3859	6	0	0
T4	45425	102	0	0
T5	5932	8	0	0
T6	16996	45	0	0
T7	3577	6	0	0
T8	3053	7	0	0
T9	1942	1	0	0
T10	1452	3	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	20916	0	0
T1	2921	6	0	0
T2	1888	1	0	0
T3	3859	6	0	0
T4	45425	102	0	0
T5	5932	8	0	0
T6	16996	45	0	0
T7	3577	6	0	0
T8	3053	7	0	0
T9	1942	1	0	0
T10	1452	3	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10760655	20916	0	0
T1	2682	6	0	0
T2	1845	1	0	0
T3	3521	6	0	0
T4	42089	102	0	0
T5	5581	8	0	0
T6	12668	45	0	0
T7	3338	6	0	0
T8	2619	7	0	0
T9	1899	1	0	0
T10	1327	3	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10760655	20916	0	0
T1	2682	6	0	0
T2	1845	1	0	0
T3	3521	6	0	0
T4	42089	102	0	0
T5	5581	8	0	0
T6	12668	45	0	0
T7	3338	6	0	0
T8	2619	7	0	0
T9	1899	1	0	0
T10	1327	3	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10760655	20916	0	0
T1	2682	6	0	0
T2	1845	1	0	0
T3	3521	6	0	0
T4	42089	102	0	0
T5	5581	8	0	0
T6	12668	45	0	0
T7	3338	6	0	0
T8	2619	7	0	0
T9	1899	1	0	0
T10	1327	3	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10760655	20916	0	0
T1	2682	6	0	0
T2	1845	1	0	0
T3	3521	6	0	0
T4	42089	102	0	0
T5	5581	8	0	0
T6	12668	45	0	0
T7	3338	6	0	0
T8	2619	7	0	0
T9	1899	1	0	0
T10	1327	3	0	0