Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T55
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T55,T57
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T55,T24,T57
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T55,T57,T48
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T55,T57,T48
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T55,T57,T48
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T55,T57
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T55,T57
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12194406	13272	0	0
gen_assertions[0].RstEnOn_A	12194406	1081	0	0
gen_assertions[0].RstNOff_A	12194406	13272	0	0
gen_assertions[0].RstNOn_A	12194406	1081	0	0
gen_assertions[1].RstEnOff_A	48777261	12048	0	0
gen_assertions[1].RstEnOn_A	48777261	1022	0	0
gen_assertions[1].RstNOff_A	48777261	12048	0	0
gen_assertions[1].RstNOn_A	48777261	1022	0	0
gen_assertions[2].RstEnOff_A	24389480	12099	0	0
gen_assertions[2].RstEnOn_A	24389480	999	0	0
gen_assertions[2].RstNOff_A	24389480	12099	0	0
gen_assertions[2].RstNOn_A	24389480	999	0	0
gen_assertions[3].RstEnOff_A	24389324	12132	0	0
gen_assertions[3].RstEnOn_A	24389324	1029	0	0
gen_assertions[3].RstNOff_A	24389324	12132	0	0
gen_assertions[3].RstNOn_A	24389324	1029	0	0
gen_assertions[4].RstEnOff_A	1539781	20766	0	0
gen_assertions[4].RstEnOn_A	1539781	1090	0	0
gen_assertions[4].RstNOff_A	1539781	20766	0	0
gen_assertions[4].RstNOn_A	1539781	1090	0	0
gen_assertions[5].RstEnOff_A	12194406	13507	0	0
gen_assertions[5].RstEnOn_A	12194406	1128	0	0
gen_assertions[5].RstNOff_A	12194406	13507	0	0
gen_assertions[5].RstNOn_A	12194406	1128	0	0
gen_assertions[6].RstEnOff_A	12194406	13572	0	0
gen_assertions[6].RstEnOn_A	12194406	1203	0	0
gen_assertions[6].RstNOff_A	12194406	13572	0	0
gen_assertions[6].RstNOn_A	12194406	1203	0	0
gen_assertions[7].RstEnOff_A	12194406	13635	0	0
gen_assertions[7].RstEnOn_A	12194406	1262	0	0
gen_assertions[7].RstNOff_A	12194406	13635	0	0
gen_assertions[7].RstNOn_A	12194406	1262	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	13272	0	0
T1	2921	5	0	0
T2	1888	0	0	0
T3	3859	4	0	0
T4	45425	75	0	0
T5	5932	0	0	0
T6	16996	32	0	0
T7	3577	4	0	0
T8	3053	6	0	0
T9	1942	0	0	0
T10	1452	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	1081	0	0
T1	2921	1	0	0
T2	1888	0	0	0
T3	3859	0	0	0
T4	45425	0	0	0
T5	5932	0	0	0
T6	16996	0	0	0
T7	3577	0	0	0
T8	3053	1	0	0
T9	1942	0	0	0
T10	1452	0	0	0
T24	0	1	0	0
T48	0	2	0	0
T50	0	5	0	0
T55	0	4	0	0
T57	0	25	0	0
T58	0	6	0	0
T66	0	7	0	0
T91	0	2	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	13272	0	0
T1	2921	5	0	0
T2	1888	0	0	0
T3	3859	4	0	0
T4	45425	75	0	0
T5	5932	0	0	0
T6	16996	32	0	0
T7	3577	4	0	0
T8	3053	6	0	0
T9	1942	0	0	0
T10	1452	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	1081	0	0
T1	2921	1	0	0
T2	1888	0	0	0
T3	3859	0	0	0
T4	45425	0	0	0
T5	5932	0	0	0
T6	16996	0	0	0
T7	3577	0	0	0
T8	3053	1	0	0
T9	1942	0	0	0
T10	1452	0	0	0
T24	0	1	0	0
T48	0	2	0	0
T50	0	5	0	0
T55	0	4	0	0
T57	0	25	0	0
T58	0	6	0	0
T66	0	7	0	0
T91	0	2	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48777261	12048	0	0
T1	11696	3	0	0
T2	7554	0	0	0
T3	15441	2	0	0
T4	181725	62	0	0
T5	23739	0	0	0
T6	67982	26	0	0
T7	14316	4	0	0
T8	12217	5	0	0
T9	7772	0	0	0
T10	5813	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48777261	1022	0	0
T10	5813	2	0	0
T11	13145	0	0	0
T12	10248	0	0	0
T13	14104	0	0	0
T14	15483	0	0	0
T24	18381	0	0	0
T31	117725	0	0	0
T40	5441	0	0	0
T41	6897	0	0	0
T48	0	2	0	0
T50	0	5	0	0
T55	40012	3	0	0
T57	0	25	0	0
T58	0	6	0	0
T66	0	8	0	0
T68	0	2	0	0
T84	0	15	0	0
T92	0	5	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48777261	12048	0	0
T1	11696	3	0	0
T2	7554	0	0	0
T3	15441	2	0	0
T4	181725	62	0	0
T5	23739	0	0	0
T6	67982	26	0	0
T7	14316	4	0	0
T8	12217	5	0	0
T9	7772	0	0	0
T10	5813	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48777261	1022	0	0
T10	5813	2	0	0
T11	13145	0	0	0
T12	10248	0	0	0
T13	14104	0	0	0
T14	15483	0	0	0
T24	18381	0	0	0
T31	117725	0	0	0
T40	5441	0	0	0
T41	6897	0	0	0
T48	0	2	0	0
T50	0	5	0	0
T55	40012	3	0	0
T57	0	25	0	0
T58	0	6	0	0
T66	0	8	0	0
T68	0	2	0	0
T84	0	15	0	0
T92	0	5	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389480	12099	0	0
T1	5843	3	0	0
T2	3777	0	0	0
T3	7720	2	0	0
T4	90864	62	0	0
T5	11867	0	0	0
T6	33993	26	0	0
T7	7157	4	0	0
T8	6108	5	0	0
T9	3886	0	0	0
T10	2906	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389480	999	0	0
T14	7741	0	0	0
T15	9113	0	0	0
T24	9190	1	0	0
T25	63834	0	0	0
T26	7098	0	0	0
T27	3171	0	0	0
T28	3353	0	0	0
T29	6599	0	0	0
T30	4532	0	0	0
T48	0	2	0	0
T55	20005	2	0	0
T57	0	20	0	0
T66	0	8	0	0
T68	0	3	0	0
T84	0	13	0	0
T92	0	6	0	0
T93	0	1	0	0
T94	0	6	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389480	12099	0	0
T1	5843	3	0	0
T2	3777	0	0	0
T3	7720	2	0	0
T4	90864	62	0	0
T5	11867	0	0	0
T6	33993	26	0	0
T7	7157	4	0	0
T8	6108	5	0	0
T9	3886	0	0	0
T10	2906	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389480	999	0	0
T14	7741	0	0	0
T15	9113	0	0	0
T24	9190	1	0	0
T25	63834	0	0	0
T26	7098	0	0	0
T27	3171	0	0	0
T28	3353	0	0	0
T29	6599	0	0	0
T30	4532	0	0	0
T48	0	2	0	0
T55	20005	2	0	0
T57	0	20	0	0
T66	0	8	0	0
T68	0	3	0	0
T84	0	13	0	0
T92	0	6	0	0
T93	0	1	0	0
T94	0	6	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389324	12132	0	0
T1	5846	3	0	0
T2	3777	0	0	0
T3	7720	2	0	0
T4	90864	62	0	0
T5	11871	0	0	0
T6	34000	26	0	0
T7	7157	4	0	0
T8	6109	5	0	0
T9	3886	0	0	0
T10	2906	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389324	1029	0	0
T14	7741	0	0	0
T15	9112	0	0	0
T24	9188	0	0	0
T25	63827	0	0	0
T26	7097	0	0	0
T27	3171	0	0	0
T28	3354	0	0	0
T29	6598	0	0	0
T30	4530	0	0	0
T48	0	4	0	0
T55	20006	4	0	0
T57	0	33	0	0
T66	0	9	0	0
T68	0	3	0	0
T84	0	14	0	0
T92	0	9	0	0
T94	0	7	0	0
T95	0	5	0	0
T96	0	13	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389324	12132	0	0
T1	5846	3	0	0
T2	3777	0	0	0
T3	7720	2	0	0
T4	90864	62	0	0
T5	11871	0	0	0
T6	34000	26	0	0
T7	7157	4	0	0
T8	6109	5	0	0
T9	3886	0	0	0
T10	2906	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24389324	1029	0	0
T14	7741	0	0	0
T15	9112	0	0	0
T24	9188	0	0	0
T25	63827	0	0	0
T26	7097	0	0	0
T27	3171	0	0	0
T28	3354	0	0	0
T29	6598	0	0	0
T30	4530	0	0	0
T48	0	4	0	0
T55	20006	4	0	0
T57	0	33	0	0
T66	0	9	0	0
T68	0	3	0	0
T84	0	14	0	0
T92	0	9	0	0
T94	0	7	0	0
T95	0	5	0	0
T96	0	13	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539781	20766	0	0
T1	364	6	0	0
T2	234	1	0	0
T3	481	5	0	0
T4	5693	88	0	0
T5	743	3	0	0
T6	2161	44	0	0
T7	447	6	0	0
T8	380	7	0	0
T9	242	1	0	0
T10	180	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539781	1090	0	0
T14	482	0	0	0
T15	568	0	0	0
T24	573	0	0	0
T25	4031	0	0	0
T26	443	0	0	0
T27	196	0	0	0
T28	209	0	0	0
T29	410	0	0	0
T30	282	0	0	0
T48	0	6	0	0
T55	1250	3	0	0
T57	0	32	0	0
T66	0	12	0	0
T68	0	5	0	0
T84	0	13	0	0
T92	0	8	0	0
T94	0	6	0	0
T95	0	5	0	0
T96	0	15	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539781	20766	0	0
T1	364	6	0	0
T2	234	1	0	0
T3	481	5	0	0
T4	5693	88	0	0
T5	743	3	0	0
T6	2161	44	0	0
T7	447	6	0	0
T8	380	7	0	0
T9	242	1	0	0
T10	180	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539781	1090	0	0
T14	482	0	0	0
T15	568	0	0	0
T24	573	0	0	0
T25	4031	0	0	0
T26	443	0	0	0
T27	196	0	0	0
T28	209	0	0	0
T29	410	0	0	0
T30	282	0	0	0
T48	0	6	0	0
T55	1250	3	0	0
T57	0	32	0	0
T66	0	12	0	0
T68	0	5	0	0
T84	0	13	0	0
T92	0	8	0	0
T94	0	6	0	0
T95	0	5	0	0
T96	0	15	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	13507	0	0
T1	2921	4	0	0
T2	1888	0	0	0
T3	3859	4	0	0
T4	45425	75	0	0
T5	5932	0	0	0
T6	16996	32	0	0
T7	3577	4	0	0
T8	3053	6	0	0
T9	1942	0	0	0
T10	1452	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	1128	0	0
T14	3869	0	0	0
T15	4556	0	0	0
T24	4594	0	0	0
T25	31917	0	0	0
T26	3548	0	0	0
T27	1585	0	0	0
T28	1676	0	0	0
T29	3298	0	0	0
T30	2264	0	0	0
T48	0	6	0	0
T55	10000	4	0	0
T57	0	23	0	0
T66	0	11	0	0
T68	0	6	0	0
T84	0	12	0	0
T89	0	1	0	0
T92	0	10	0	0
T94	0	7	0	0
T95	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	13507	0	0
T1	2921	4	0	0
T2	1888	0	0	0
T3	3859	4	0	0
T4	45425	75	0	0
T5	5932	0	0	0
T6	16996	32	0	0
T7	3577	4	0	0
T8	3053	6	0	0
T9	1942	0	0	0
T10	1452	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	1128	0	0
T14	3869	0	0	0
T15	4556	0	0	0
T24	4594	0	0	0
T25	31917	0	0	0
T26	3548	0	0	0
T27	1585	0	0	0
T28	1676	0	0	0
T29	3298	0	0	0
T30	2264	0	0	0
T48	0	6	0	0
T55	10000	4	0	0
T57	0	23	0	0
T66	0	11	0	0
T68	0	6	0	0
T84	0	12	0	0
T89	0	1	0	0
T92	0	10	0	0
T94	0	7	0	0
T95	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	13572	0	0
T1	2921	5	0	0
T2	1888	0	0	0
T3	3859	4	0	0
T4	45425	75	0	0
T5	5932	0	0	0
T6	16996	32	0	0
T7	3577	4	0	0
T8	3053	6	0	0
T9	1942	0	0	0
T10	1452	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	1203	0	0
T1	2921	1	0	0
T2	1888	0	0	0
T3	3859	0	0	0
T4	45425	0	0	0
T5	5932	0	0	0
T6	16996	0	0	0
T7	3577	0	0	0
T8	3053	0	0	0
T9	1942	0	0	0
T10	1452	0	0	0
T48	0	7	0	0
T55	0	5	0	0
T57	0	27	0	0
T66	0	14	0	0
T68	0	7	0	0
T84	0	11	0	0
T89	0	1	0	0
T92	0	11	0	0
T93	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	13572	0	0
T1	2921	5	0	0
T2	1888	0	0	0
T3	3859	4	0	0
T4	45425	75	0	0
T5	5932	0	0	0
T6	16996	32	0	0
T7	3577	4	0	0
T8	3053	6	0	0
T9	1942	0	0	0
T10	1452	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	1203	0	0
T1	2921	1	0	0
T2	1888	0	0	0
T3	3859	0	0	0
T4	45425	0	0	0
T5	5932	0	0	0
T6	16996	0	0	0
T7	3577	0	0	0
T8	3053	0	0	0
T9	1942	0	0	0
T10	1452	0	0	0
T48	0	7	0	0
T55	0	5	0	0
T57	0	27	0	0
T66	0	14	0	0
T68	0	7	0	0
T84	0	11	0	0
T89	0	1	0	0
T92	0	11	0	0
T93	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	13635	0	0
T1	2921	5	0	0
T2	1888	0	0	0
T3	3859	4	0	0
T4	45425	75	0	0
T5	5932	0	0	0
T6	16996	32	0	0
T7	3577	4	0	0
T8	3053	6	0	0
T9	1942	0	0	0
T10	1452	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	1262	0	0
T1	2921	1	0	0
T2	1888	0	0	0
T3	3859	0	0	0
T4	45425	0	0	0
T5	5932	0	0	0
T6	16996	0	0	0
T7	3577	0	0	0
T8	3053	0	0	0
T9	1942	0	0	0
T10	1452	0	0	0
T48	0	9	0	0
T55	0	3	0	0
T57	0	31	0	0
T66	0	13	0	0
T68	0	8	0	0
T84	0	14	0	0
T92	0	11	0	0
T93	0	1	0	0
T94	0	5	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	13635	0	0
T1	2921	5	0	0
T2	1888	0	0	0
T3	3859	4	0	0
T4	45425	75	0	0
T5	5932	0	0	0
T6	16996	32	0	0
T7	3577	4	0	0
T8	3053	6	0	0
T9	1942	0	0	0
T10	1452	2	0	0
T11	0	4	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12194406	1262	0	0
T1	2921	1	0	0
T2	1888	0	0	0
T3	3859	0	0	0
T4	45425	0	0	0
T5	5932	0	0	0
T6	16996	0	0	0
T7	3577	0	0	0
T8	3053	0	0	0
T9	1942	0	0	0
T10	1452	0	0	0
T48	0	9	0	0
T55	0	3	0	0
T57	0	31	0	0
T66	0	13	0	0
T68	0	8	0	0
T84	0	14	0	0
T92	0	11	0	0
T93	0	1	0	0
T94	0	5	0	0