Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11572028	5876	0	0
alert_regwen_rd_A	11572028	4612	0	0
cpu_regwen_rd_A	11572028	4599	0	0
sw_rst_ctrl_n_0_rd_A	11572028	7171	0	0
sw_rst_ctrl_n_1_rd_A	11572028	7447	0	0
sw_rst_ctrl_n_2_rd_A	11572028	7144	0	0
sw_rst_ctrl_n_3_rd_A	11572028	7323	0	0
sw_rst_ctrl_n_4_rd_A	11572028	7054	0	0
sw_rst_ctrl_n_5_rd_A	11572028	6721	0	0
sw_rst_ctrl_n_6_rd_A	11572028	7084	0	0
sw_rst_ctrl_n_7_rd_A	11572028	7172	0	0
sw_rst_regwen_0_rd_A	11572028	4979	0	0
sw_rst_regwen_1_rd_A	11572028	5065	0	0
sw_rst_regwen_2_rd_A	11572028	4874	0	0
sw_rst_regwen_3_rd_A	11572028	5023	0	0
sw_rst_regwen_4_rd_A	11572028	5274	0	0
sw_rst_regwen_5_rd_A	11572028	5327	0	0
sw_rst_regwen_6_rd_A	11572028	5061	0	0
sw_rst_regwen_7_rd_A	11572028	4961	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	5876	0	0
T71	2427	83	0	0
T72	2095	2	0	0
T73	21521	1	0	0
T75	10276	1	0	0
T76	5694	248	0	0
T77	5609	85	0	0
T97	2300	6	0	0
T98	3093	170	0	0
T99	4289	9	0	0
T101	11021	540	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	4612	0	0
T15	4417	0	0	0
T16	4269	0	0	0
T17	4140	0	0	0
T25	27773	29	0	0
T26	3304	0	0	0
T27	1566	0	0	0
T28	1482	0	0	0
T29	3007	0	0	0
T30	2118	0	0	0
T56	14119	0	0	0
T104	0	32	0	0
T109	0	74	0	0
T110	0	81	0	0
T111	0	82	0	0
T113	0	39	0	0
T114	0	41	0	0
T117	0	42	0	0
T139	0	29	0	0
T140	0	79	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	4599	0	0
T15	4417	0	0	0
T16	4269	0	0	0
T17	4140	0	0	0
T25	27773	18	0	0
T26	3304	0	0	0
T27	1566	0	0	0
T28	1482	0	0	0
T29	3007	0	0	0
T30	2118	0	0	0
T56	14119	0	0	0
T104	0	27	0	0
T109	0	98	0	0
T110	0	78	0	0
T111	0	68	0	0
T113	0	41	0	0
T114	0	57	0	0
T117	0	46	0	0
T139	0	33	0	0
T140	0	51	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	7171	0	0
T8	2619	22	0	0
T9	1899	0	0	0
T10	1327	0	0	0
T11	3090	0	0	0
T12	2223	0	0	0
T13	3379	0	0	0
T25	0	18	0	0
T28	0	1	0	0
T31	26056	0	0	0
T40	1293	0	0	0
T41	1705	0	0	0
T48	0	53	0	0
T55	9839	39	0	0
T66	0	92	0	0
T85	0	7	0	0
T92	0	161	0	0
T104	0	12	0	0
T141	0	38	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	7447	0	0
T8	2619	8	0	0
T9	1899	0	0	0
T10	1327	0	0	0
T11	3090	0	0	0
T12	2223	0	0	0
T13	3379	0	0	0
T25	0	21	0	0
T28	0	1	0	0
T31	26056	0	0	0
T40	1293	0	0	0
T41	1705	0	0	0
T48	0	96	0	0
T55	9839	64	0	0
T66	0	103	0	0
T85	0	7	0	0
T92	0	178	0	0
T104	0	24	0	0
T141	0	54	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	7144	0	0
T8	2619	19	0	0
T9	1899	0	0	0
T10	1327	0	0	0
T11	3090	0	0	0
T12	2223	0	0	0
T13	3379	0	0	0
T25	0	27	0	0
T28	0	6	0	0
T31	26056	0	0	0
T40	1293	0	0	0
T41	1705	0	0	0
T48	0	82	0	0
T55	9839	70	0	0
T66	0	129	0	0
T92	0	191	0	0
T104	0	26	0	0
T141	0	63	0	0
T142	0	20	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	7323	0	0
T8	2619	27	0	0
T9	1899	0	0	0
T10	1327	0	0	0
T11	3090	0	0	0
T12	2223	0	0	0
T13	3379	0	0	0
T25	0	48	0	0
T28	0	9	0	0
T31	26056	0	0	0
T40	1293	0	0	0
T41	1705	0	0	0
T48	0	102	0	0
T55	9839	70	0	0
T66	0	122	0	0
T85	0	6	0	0
T92	0	171	0	0
T104	0	22	0	0
T141	0	48	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	7054	0	0
T8	2619	16	0	0
T9	1899	0	0	0
T10	1327	0	0	0
T11	3090	0	0	0
T12	2223	0	0	0
T13	3379	0	0	0
T25	0	10	0	0
T28	0	3	0	0
T31	26056	0	0	0
T40	1293	0	0	0
T41	1705	0	0	0
T48	0	58	0	0
T55	9839	55	0	0
T66	0	106	0	0
T85	0	3	0	0
T92	0	149	0	0
T104	0	20	0	0
T141	0	43	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	6721	0	0
T8	2619	36	0	0
T9	1899	0	0	0
T10	1327	0	0	0
T11	3090	0	0	0
T12	2223	0	0	0
T13	3379	0	0	0
T25	0	15	0	0
T28	0	2	0	0
T31	26056	0	0	0
T40	1293	0	0	0
T41	1705	0	0	0
T48	0	80	0	0
T55	9839	49	0	0
T66	0	100	0	0
T85	0	6	0	0
T92	0	175	0	0
T104	0	26	0	0
T141	0	38	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	7084	0	0
T8	2619	14	0	0
T9	1899	0	0	0
T10	1327	0	0	0
T11	3090	0	0	0
T12	2223	0	0	0
T13	3379	0	0	0
T25	0	31	0	0
T28	0	9	0	0
T31	26056	0	0	0
T40	1293	0	0	0
T41	1705	0	0	0
T48	0	83	0	0
T55	9839	87	0	0
T66	0	104	0	0
T85	0	2	0	0
T92	0	153	0	0
T104	0	36	0	0
T141	0	56	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	7172	0	0
T8	2619	22	0	0
T9	1899	0	0	0
T10	1327	0	0	0
T11	3090	0	0	0
T12	2223	0	0	0
T13	3379	0	0	0
T25	0	23	0	0
T28	0	3	0	0
T31	26056	0	0	0
T40	1293	0	0	0
T41	1705	0	0	0
T48	0	71	0	0
T55	9839	57	0	0
T66	0	126	0	0
T92	0	144	0	0
T104	0	29	0	0
T141	0	56	0	0
T142	0	12	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	4979	0	0
T15	4417	0	0	0
T16	4269	0	0	0
T17	4140	0	0	0
T25	27773	15	0	0
T26	3304	0	0	0
T27	1566	0	0	0
T28	1482	0	0	0
T29	3007	0	0	0
T30	2118	0	0	0
T48	0	8	0	0
T56	14119	0	0	0
T66	0	18	0	0
T92	0	38	0	0
T104	0	22	0	0
T109	0	83	0	0
T117	0	38	0	0
T142	0	12	0	0
T143	0	15	0	0
T144	0	19	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	5065	0	0
T15	4417	0	0	0
T16	4269	0	0	0
T17	4140	0	0	0
T25	27773	29	0	0
T26	3304	0	0	0
T27	1566	0	0	0
T28	1482	0	0	0
T29	3007	0	0	0
T30	2118	0	0	0
T48	0	17	0	0
T56	14119	0	0	0
T66	0	25	0	0
T92	0	23	0	0
T104	0	33	0	0
T109	0	76	0	0
T117	0	33	0	0
T142	0	11	0	0
T143	0	14	0	0
T144	0	26	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	4874	0	0
T15	4417	0	0	0
T16	4269	0	0	0
T17	4140	0	0	0
T25	27773	18	0	0
T26	3304	0	0	0
T27	1566	0	0	0
T28	1482	0	0	0
T29	3007	0	0	0
T30	2118	0	0	0
T48	0	25	0	0
T56	14119	0	0	0
T66	0	12	0	0
T92	0	37	0	0
T104	0	43	0	0
T109	0	85	0	0
T117	0	11	0	0
T142	0	5	0	0
T143	0	1	0	0
T144	0	21	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	5023	0	0
T15	4417	0	0	0
T16	4269	0	0	0
T17	4140	0	0	0
T25	27773	26	0	0
T26	3304	0	0	0
T27	1566	0	0	0
T28	1482	0	0	0
T29	3007	0	0	0
T30	2118	0	0	0
T48	0	9	0	0
T56	14119	0	0	0
T66	0	30	0	0
T92	0	42	0	0
T104	0	28	0	0
T109	0	71	0	0
T117	0	37	0	0
T142	0	7	0	0
T143	0	3	0	0
T144	0	18	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	5274	0	0
T15	4417	0	0	0
T16	4269	0	0	0
T17	4140	0	0	0
T25	27773	24	0	0
T26	3304	0	0	0
T27	1566	0	0	0
T28	1482	0	0	0
T29	3007	0	0	0
T30	2118	0	0	0
T48	0	12	0	0
T56	14119	0	0	0
T66	0	12	0	0
T92	0	41	0	0
T104	0	23	0	0
T109	0	70	0	0
T117	0	28	0	0
T142	0	5	0	0
T143	0	11	0	0
T144	0	21	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	5327	0	0
T15	4417	0	0	0
T16	4269	0	0	0
T17	4140	0	0	0
T25	27773	34	0	0
T26	3304	0	0	0
T27	1566	0	0	0
T28	1482	0	0	0
T29	3007	0	0	0
T30	2118	0	0	0
T48	0	14	0	0
T56	14119	0	0	0
T66	0	16	0	0
T92	0	34	0	0
T104	0	32	0	0
T109	0	70	0	0
T117	0	30	0	0
T142	0	5	0	0
T143	0	17	0	0
T144	0	31	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	5061	0	0
T15	4417	0	0	0
T16	4269	0	0	0
T17	4140	0	0	0
T25	27773	19	0	0
T26	3304	0	0	0
T27	1566	0	0	0
T28	1482	0	0	0
T29	3007	0	0	0
T30	2118	0	0	0
T48	0	18	0	0
T56	14119	0	0	0
T66	0	21	0	0
T92	0	34	0	0
T104	0	34	0	0
T109	0	86	0	0
T117	0	32	0	0
T142	0	4	0	0
T143	0	7	0	0
T144	0	26	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11572028	4961	0	0
T15	4417	0	0	0
T16	4269	0	0	0
T17	4140	0	0	0
T25	27773	18	0	0
T26	3304	0	0	0
T27	1566	0	0	0
T28	1482	0	0	0
T29	3007	0	0	0
T30	2118	0	0	0
T48	0	3	0	0
T56	14119	0	0	0
T66	0	11	0	0
T92	0	26	0	0
T104	0	21	0	0
T109	0	83	0	0
T117	0	32	0	0
T142	0	3	0	0
T143	0	7	0	0
T144	0	27	0	0