Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	600739	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

360251

1

T2

1119

T3

133

T4

799

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	513086	1			T2	1500		T3	186		T4	1260
values[0x0]	223651	1			T2	853		T3	78		T4	498
values[0x1]	224253	1			T2	847		T3	115		T4	502

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	504284	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

456706

1

T2

1440

T3

177

T4

1048

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4315	1			T2	16		T4	10		T5	1
valid_sources[0x01]	3005	1			T2	12		T4	8		T8	8
valid_sources[0x02]	3235	1			T2	16		T4	10		T5	2
valid_sources[0x03]	4424	1			T2	20		T4	6		T8	15
valid_sources[0x04]	3714	1			T2	4		T4	13		T6	25
valid_sources[0x05]	3997	1			T2	7		T4	7		T5	2
valid_sources[0x06]	3023	1			T2	24		T4	5		T5	1
valid_sources[0x07]	3210	1			T2	9		T4	3		T8	14
valid_sources[0x08]	4097	1			T2	19		T4	3		T5	1
valid_sources[0x09]	2966	1			T2	12		T4	2		T8	10
valid_sources[0x0a]	4610	1			T2	12		T4	11		T5	2
valid_sources[0x0b]	3888	1			T2	30		T4	16		T5	1
valid_sources[0x0c]	2728	1			T2	14		T4	11		T5	1
valid_sources[0x0d]	3101	1			T2	6		T4	10		T8	6
valid_sources[0x0e]	3330	1			T2	34		T4	8		T6	2
valid_sources[0x0f]	3779	1			T2	17		T4	11		T8	17
valid_sources[0x10]	3118	1			T2	14		T4	3		T6	14
valid_sources[0x11]	3174	1			T2	9		T4	8		T5	6
valid_sources[0x12]	4066	1			T2	16		T4	6		T5	1
valid_sources[0x13]	3922	1			T2	14		T4	9		T5	2
valid_sources[0x14]	2883	1			T2	7		T4	8		T8	6
valid_sources[0x15]	3333	1			T2	2		T4	7		T5	4
valid_sources[0x16]	2850	1			T2	9		T3	19		T4	18
valid_sources[0x17]	3186	1			T2	14		T4	7		T6	11
valid_sources[0x18]	3268	1			T2	21		T4	4		T6	3
valid_sources[0x19]	3291	1			T2	20		T4	10		T6	2
valid_sources[0x1a]	3133	1			T2	16		T4	7		T8	15
valid_sources[0x1b]	5433	1			T2	15		T4	11		T6	8
valid_sources[0x1c]	3410	1			T2	19		T4	5		T5	1
valid_sources[0x1d]	3820	1			T2	13		T3	12		T4	6
valid_sources[0x1e]	2751	1			T2	1		T4	5		T6	9
valid_sources[0x1f]	3864	1			T2	11		T4	9		T5	4
valid_sources[0x20]	4671	1			T2	28		T4	4		T5	1
valid_sources[0x21]	3159	1			T2	6		T4	13		T6	3
valid_sources[0x22]	3090	1			T2	19		T4	11		T5	2
valid_sources[0x23]	3513	1			T2	2		T3	44		T4	8
valid_sources[0x24]	3164	1			T2	10		T4	12		T5	1
valid_sources[0x25]	3574	1			T2	10		T4	9		T5	3
valid_sources[0x26]	7088	1			T2	9		T3	3		T4	15
valid_sources[0x27]	6938	1			T2	3		T4	5		T5	2
valid_sources[0x28]	3265	1			T2	25		T4	7		T6	2
valid_sources[0x29]	4454	1			T2	12		T4	12		T8	15
valid_sources[0x2a]	3364	1			T2	7		T4	10		T8	12
valid_sources[0x2b]	3723	1			T2	3		T4	20		T6	13
valid_sources[0x2c]	3258	1			T2	7		T4	2		T6	4
valid_sources[0x2d]	6431	1			T2	17		T4	7		T8	12
valid_sources[0x2e]	4056	1			T2	10		T4	7		T5	4
valid_sources[0x2f]	3158	1			T2	5		T4	11		T5	1
valid_sources[0x30]	3576	1			T2	5		T4	7		T8	13
valid_sources[0x31]	3065	1			T2	11		T4	18		T5	1
valid_sources[0x32]	2970	1			T2	21		T4	2		T5	1
valid_sources[0x33]	3814	1			T2	18		T4	11		T5	2
valid_sources[0x34]	5346	1			T2	14		T4	16		T6	4
valid_sources[0x35]	5119	1			T2	16		T4	13		T6	5
valid_sources[0x36]	3589	1			T2	8		T4	9		T8	11
valid_sources[0x37]	3354	1			T2	6		T4	8		T8	13
valid_sources[0x38]	3645	1			T2	17		T4	11		T5	1
valid_sources[0x39]	3512	1			T2	17		T4	5		T6	1
valid_sources[0x3a]	3212	1			T2	8		T4	9		T5	2
valid_sources[0x3b]	3515	1			T2	11		T3	27		T4	13
valid_sources[0x3c]	3444	1			T2	17		T4	11		T6	3
valid_sources[0x3d]	3625	1			T2	15		T4	8		T5	1
valid_sources[0x3e]	3074	1			T2	12		T4	8		T5	1
valid_sources[0x3f]	3523	1			T2	17		T4	3		T5	2
valid_sources[0x40]	3144	1			T2	17		T4	9		T5	1
valid_sources[0x41]	4201	1			T2	14		T4	7		T6	3
valid_sources[0x42]	3509	1			T2	7		T4	5		T6	2
valid_sources[0x43]	3385	1			T2	14		T4	2		T5	2
valid_sources[0x44]	3416	1			T2	9		T4	8		T5	1
valid_sources[0x45]	3219	1			T2	8		T4	9		T5	1
valid_sources[0x46]	3741	1			T2	11		T3	9		T4	1
valid_sources[0x47]	3712	1			T2	20		T3	9		T4	4
valid_sources[0x48]	2749	1			T2	28		T4	16		T6	2
valid_sources[0x49]	3319	1			T2	5		T4	8		T5	1
valid_sources[0x4a]	4335	1			T2	12		T4	21		T5	4
valid_sources[0x4b]	3614	1			T2	15		T4	9		T6	8
valid_sources[0x4c]	2844	1			T2	8		T4	7		T6	14
valid_sources[0x4d]	3236	1			T2	4		T4	2		T5	2
valid_sources[0x4e]	3135	1			T2	16		T4	16		T6	12
valid_sources[0x4f]	4836	1			T2	14		T4	2		T6	5
valid_sources[0x50]	3656	1			T2	23		T4	6		T5	1
valid_sources[0x51]	4096	1			T2	16		T4	10		T6	2
valid_sources[0x52]	4925	1			T2	20		T4	12		T5	1
valid_sources[0x53]	4072	1			T2	11		T4	5		T5	1
valid_sources[0x54]	4370	1			T2	14		T4	3		T5	1
valid_sources[0x55]	3735	1			T2	22		T4	13		T8	4
valid_sources[0x56]	3886	1			T2	15		T3	1		T4	16
valid_sources[0x57]	2877	1			T2	14		T4	15		T5	1
valid_sources[0x58]	5985	1			T2	10		T4	11		T6	9
valid_sources[0x59]	3392	1			T2	30		T4	12		T5	1
valid_sources[0x5a]	4049	1			T2	27		T4	9		T5	1
valid_sources[0x5b]	2841	1			T2	12		T4	7		T5	1
valid_sources[0x5c]	2959	1			T2	7		T4	8		T6	10
valid_sources[0x5d]	3141	1			T2	9		T4	5		T6	1
valid_sources[0x5e]	3322	1			T2	20		T4	7		T5	2
valid_sources[0x5f]	3884	1			T2	11		T4	3		T8	18
valid_sources[0x60]	2993	1			T2	17		T4	14		T5	1
valid_sources[0x61]	3346	1			T2	13		T4	6		T6	1
valid_sources[0x62]	3642	1			T2	2		T4	18		T5	2
valid_sources[0x63]	2748	1			T2	5		T4	6		T6	5
valid_sources[0x64]	3526	1			T2	11		T4	4		T5	1
valid_sources[0x65]	3105	1			T2	12		T4	11		T5	1
valid_sources[0x66]	3225	1			T2	12		T4	9		T6	7
valid_sources[0x67]	3324	1			T2	13		T4	9		T6	6
valid_sources[0x68]	4314	1			T2	8		T4	6		T8	7
valid_sources[0x69]	3043	1			T2	28		T4	6		T6	5
valid_sources[0x6a]	3061	1			T2	14		T4	5		T8	8
valid_sources[0x6b]	3772	1			T2	6		T4	9		T8	15
valid_sources[0x6c]	3192	1			T2	8		T4	5		T6	5
valid_sources[0x6d]	3456	1			T2	7		T4	6		T6	7
valid_sources[0x6e]	3347	1			T2	19		T4	2		T8	11
valid_sources[0x6f]	3490	1			T2	6		T4	17		T5	2
valid_sources[0x70]	4857	1			T2	7		T4	6		T5	1
valid_sources[0x71]	2972	1			T2	6		T4	9		T5	1
valid_sources[0x72]	3520	1			T2	13		T4	13		T5	2
valid_sources[0x73]	2797	1			T2	9		T4	17		T6	8
valid_sources[0x74]	3696	1			T2	21		T4	4		T5	1
valid_sources[0x75]	3742	1			T2	18		T3	18		T4	14
valid_sources[0x76]	4001	1			T2	10		T4	9		T8	7
valid_sources[0x77]	2802	1			T2	19		T4	1		T6	3
valid_sources[0x78]	3686	1			T2	9		T4	7		T6	3
valid_sources[0x79]	4586	1			T2	12		T4	9		T8	13
valid_sources[0x7a]	4109	1			T2	11		T4	11		T8	14
valid_sources[0x7b]	3165	1			T2	16		T3	43		T4	5
valid_sources[0x7c]	2919	1			T2	14		T4	13		T6	2
valid_sources[0x7d]	3827	1			T2	8		T4	12		T5	1
valid_sources[0x7e]	3426	1			T2	14		T4	11		T5	1
valid_sources[0x7f]	3311	1			T2	14		T4	14		T5	2
valid_sources[0x80]	4195	1			T2	9		T4	5		T8	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

240593

1

T2

712

T3

92

T4

561

values[0x0]

all_enables

biggest_size

77859

1

T2

279

T3

23

T4

154

values[0x1]

all_enables

biggest_size

41799

1

T2

128

T3

18

T4

84