Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	10354890	12740	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	10354890	117584	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	10354890	6042314	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	10354890	187398	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	10354890	12740	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	10354890	117584	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	10354890	6042314	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	10354890	187398	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	12740	0	0
T2	26110	75	0	0
T3	4250	4	0	0
T4	13560	30	0	0
T5	4076	4	0	0
T6	11939	0	0	0
T7	2751	4	0	0
T8	18943	39	0	0
T9	288237	241	0	0
T10	17247	38	0	0
T11	3168	0	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	117584	0	0
T2	26110	700	0	0
T3	4250	37	0	0
T4	13560	277	0	0
T5	4076	37	0	0
T6	11939	0	0	0
T7	2751	37	0	0
T8	18943	360	0	0
T9	288237	2227	0	0
T10	17247	346	0	0
T11	3168	0	0	0
T12	0	38	0	0
T13	0	38	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	6042314	0	0
T1	5085	574	0	0
T2	26110	8716	0	0
T3	4250	3277	0	0
T4	13560	6291	0	0
T5	4076	3134	0	0
T6	11939	11287	0	0
T7	2751	1763	0	0
T8	18943	8816	0	0
T9	288237	228256	0	0
T10	17247	7984	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	187398	0	0
T2	26110	1149	0	0
T3	4250	72	0	0
T4	13560	433	0	0
T5	4076	63	0	0
T6	11939	0	0	0
T7	2751	64	0	0
T8	18943	615	0	0
T9	288237	3614	0	0
T10	17247	538	0	0
T11	3168	0	0	0
T12	0	61	0	0
T13	0	60	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	12740	0	0
T2	26110	75	0	0
T3	4250	4	0	0
T4	13560	30	0	0
T5	4076	4	0	0
T6	11939	0	0	0
T7	2751	4	0	0
T8	18943	39	0	0
T9	288237	241	0	0
T10	17247	38	0	0
T11	3168	0	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	117584	0	0
T2	26110	700	0	0
T3	4250	37	0	0
T4	13560	277	0	0
T5	4076	37	0	0
T6	11939	0	0	0
T7	2751	37	0	0
T8	18943	360	0	0
T9	288237	2227	0	0
T10	17247	346	0	0
T11	3168	0	0	0
T12	0	38	0	0
T13	0	38	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	6042314	0	0
T1	5085	574	0	0
T2	26110	8716	0	0
T3	4250	3277	0	0
T4	13560	6291	0	0
T5	4076	3134	0	0
T6	11939	11287	0	0
T7	2751	1763	0	0
T8	18943	8816	0	0
T9	288237	228256	0	0
T10	17247	7984	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	187398	0	0
T2	26110	1149	0	0
T3	4250	72	0	0
T4	13560	433	0	0
T5	4076	63	0	0
T6	11939	0	0	0
T7	2751	64	0	0
T8	18943	615	0	0
T9	288237	3614	0	0
T10	17247	538	0	0
T11	3168	0	0	0
T12	0	61	0	0
T13	0	60	0	0