Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T4,T5,T8
1	0	Covered	T3,T4,T7

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	48876205	7945	0	0
CascadeEffAonToRstPorAboveRise_A	48876205	7945	0	0
CascadeEffAonToRstPorIoAboveFall_A	46920200	7945	0	0
CascadeEffAonToRstPorIoAboveRise_A	46920200	7945	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	23460933	7945	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	23460933	7945	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	11729989	7945	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	11729989	7945	0	0
CascadeEffAonToRstPorUcbAboveFall_A	23460701	7945	0	0
CascadeEffAonToRstPorUcbAboveRise_A	23460701	7945	0	0
CascadeLcToLcAboveFall_A	48876205	20685	0	0
CascadeLcToLcAboveRise_A	48876205	20685	0	0
CascadeLcToLcAonAboveFall_A	1482077	20685	0	0
CascadeLcToLcAonAboveRise_A	1482077	20685	0	0
CascadeLcToLcShadowedAboveFall_A	48876205	20685	0	0
CascadeLcToLcShadowedAboveRise_A	48876205	20685	0	0
CascadePorToAonAboveFall_A	1482077	6263	0	0
CascadeSysToSysAboveFall_A	48876205	20685	0	0
CascadeSysToSysAboveRise_A	48876205	20685	0	0
ScanRstToAonRise_A	1482077	194	0	0
StablePorToAonRise_A	1482077	7945	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10354890	20685	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10354890	20685	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10354890	20685	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10354890	20685	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	11729989	20685	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	11729989	20685	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10354890	20685	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10354890	20685	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10354890	20685	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10354890	20685	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48876205	7945	0	0
T1	24259	8	0	0
T2	121528	27	0	0
T3	19112	2	0	0
T4	72965	15	0	0
T5	18601	2	0	0
T6	49830	1	0	0
T7	12053	2	0	0
T8	97313	22	0	0
T9	133313	128	0	0
T10	93770	20	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48876205	7945	0	0
T1	24259	8	0	0
T2	121528	27	0	0
T3	19112	2	0	0
T4	72965	15	0	0
T5	18601	2	0	0
T6	49830	1	0	0
T7	12053	2	0	0
T8	97313	22	0	0
T9	133313	128	0	0
T10	93770	20	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46920200	7945	0	0
T1	23277	8	0	0
T2	116679	27	0	0
T3	18347	2	0	0
T4	70024	15	0	0
T5	17852	2	0	0
T6	47833	1	0	0
T7	11569	2	0	0
T8	93432	22	0	0
T9	127980	128	0	0
T10	90010	20	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46920200	7945	0	0
T1	23277	8	0	0
T2	116679	27	0	0
T3	18347	2	0	0
T4	70024	15	0	0
T5	17852	2	0	0
T6	47833	1	0	0
T7	11569	2	0	0
T8	93432	22	0	0
T9	127980	128	0	0
T10	90010	20	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460933	7945	0	0
T1	11636	8	0	0
T2	58338	27	0	0
T3	9174	2	0	0
T4	35018	15	0	0
T5	8928	2	0	0
T6	23917	1	0	0
T7	5784	2	0	0
T8	46727	22	0	0
T9	639935	128	0	0
T10	45011	20	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460933	7945	0	0
T1	11636	8	0	0
T2	58338	27	0	0
T3	9174	2	0	0
T4	35018	15	0	0
T5	8928	2	0	0
T6	23917	1	0	0
T7	5784	2	0	0
T8	46727	22	0	0
T9	639935	128	0	0
T10	45011	20	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	7945	0	0
T1	5824	8	0	0
T2	29160	27	0	0
T3	4588	2	0	0
T4	17506	15	0	0
T5	4462	2	0	0
T6	11957	1	0	0
T7	2892	2	0	0
T8	23355	22	0	0
T9	319976	128	0	0
T10	22503	20	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	7945	0	0
T1	5824	8	0	0
T2	29160	27	0	0
T3	4588	2	0	0
T4	17506	15	0	0
T5	4462	2	0	0
T6	11957	1	0	0
T7	2892	2	0	0
T8	23355	22	0	0
T9	319976	128	0	0
T10	22503	20	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460701	7945	0	0
T1	11644	8	0	0
T2	58322	27	0	0
T3	9175	2	0	0
T4	35024	15	0	0
T5	8925	2	0	0
T6	23917	1	0	0
T7	5784	2	0	0
T8	46723	22	0	0
T9	639921	128	0	0
T10	45015	20	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460701	7945	0	0
T1	11644	8	0	0
T2	58322	27	0	0
T3	9175	2	0	0
T4	35024	15	0	0
T5	8925	2	0	0
T6	23917	1	0	0
T7	5784	2	0	0
T8	46723	22	0	0
T9	639921	128	0	0
T10	45015	20	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48876205	20685	0	0
T1	24259	8	0	0
T2	121528	102	0	0
T3	19112	6	0	0
T4	72965	45	0	0
T5	18601	6	0	0
T6	49830	1	0	0
T7	12053	6	0	0
T8	97313	61	0	0
T9	133313	369	0	0
T10	93770	58	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48876205	20685	0	0
T1	24259	8	0	0
T2	121528	102	0	0
T3	19112	6	0	0
T4	72965	45	0	0
T5	18601	6	0	0
T6	49830	1	0	0
T7	12053	6	0	0
T8	97313	61	0	0
T9	133313	369	0	0
T10	93770	58	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482077	20685	0	0
T1	730	8	0	0
T2	3660	102	0	0
T3	572	6	0	0
T4	2224	45	0	0
T5	556	6	0	0
T6	1492	1	0	0
T7	361	6	0	0
T8	2991	61	0	0
T9	40393	369	0	0
T10	2910	58	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482077	20685	0	0
T1	730	8	0	0
T2	3660	102	0	0
T3	572	6	0	0
T4	2224	45	0	0
T5	556	6	0	0
T6	1492	1	0	0
T7	361	6	0	0
T8	2991	61	0	0
T9	40393	369	0	0
T10	2910	58	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48876205	20685	0	0
T1	24259	8	0	0
T2	121528	102	0	0
T3	19112	6	0	0
T4	72965	45	0	0
T5	18601	6	0	0
T6	49830	1	0	0
T7	12053	6	0	0
T8	97313	61	0	0
T9	133313	369	0	0
T10	93770	58	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48876205	20685	0	0
T1	24259	8	0	0
T2	121528	102	0	0
T3	19112	6	0	0
T4	72965	45	0	0
T5	18601	6	0	0
T6	49830	1	0	0
T7	12053	6	0	0
T8	97313	61	0	0
T9	133313	369	0	0
T10	93770	58	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482077	6263	0	0
T1	730	8	0	0
T2	3660	27	0	0
T3	572	1	0	0
T4	2224	9	0	0
T5	556	1	0	0
T6	1492	1	0	0
T7	361	1	0	0
T8	2991	11	0	0
T9	40393	69	0	0
T10	2910	11	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48876205	20685	0	0
T1	24259	8	0	0
T2	121528	102	0	0
T3	19112	6	0	0
T4	72965	45	0	0
T5	18601	6	0	0
T6	49830	1	0	0
T7	12053	6	0	0
T8	97313	61	0	0
T9	133313	369	0	0
T10	93770	58	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48876205	20685	0	0
T1	24259	8	0	0
T2	121528	102	0	0
T3	19112	6	0	0
T4	72965	45	0	0
T5	18601	6	0	0
T6	49830	1	0	0
T7	12053	6	0	0
T8	97313	61	0	0
T9	133313	369	0	0
T10	93770	58	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482077	194	0	0
T4	2224	2	0	0
T5	556	1	0	0
T6	1492	0	0	0
T7	361	0	0	0
T8	2991	2	0	0
T9	40393	5	0	0
T10	2910	2	0	0
T11	399	0	0	0
T12	427	0	0	0
T13	330	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T76	0	2	0	0
T85	0	1	0	0
T127	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482077	7945	0	0
T1	730	8	0	0
T2	3660	27	0	0
T3	572	2	0	0
T4	2224	15	0	0
T5	556	2	0	0
T6	1492	1	0	0
T7	361	2	0	0
T8	2991	22	0	0
T9	40393	128	0	0
T10	2910	20	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	20685	0	0
T1	5085	8	0	0
T2	26110	102	0	0
T3	4250	6	0	0
T4	13560	45	0	0
T5	4076	6	0	0
T6	11939	1	0	0
T7	2751	6	0	0
T8	18943	61	0	0
T9	288237	369	0	0
T10	17247	58	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	20685	0	0
T1	5085	8	0	0
T2	26110	102	0	0
T3	4250	6	0	0
T4	13560	45	0	0
T5	4076	6	0	0
T6	11939	1	0	0
T7	2751	6	0	0
T8	18943	61	0	0
T9	288237	369	0	0
T10	17247	58	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	20685	0	0
T1	5085	8	0	0
T2	26110	102	0	0
T3	4250	6	0	0
T4	13560	45	0	0
T5	4076	6	0	0
T6	11939	1	0	0
T7	2751	6	0	0
T8	18943	61	0	0
T9	288237	369	0	0
T10	17247	58	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	20685	0	0
T1	5085	8	0	0
T2	26110	102	0	0
T3	4250	6	0	0
T4	13560	45	0	0
T5	4076	6	0	0
T6	11939	1	0	0
T7	2751	6	0	0
T8	18943	61	0	0
T9	288237	369	0	0
T10	17247	58	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	20685	0	0
T1	5824	8	0	0
T2	29160	102	0	0
T3	4588	6	0	0
T4	17506	45	0	0
T5	4462	6	0	0
T6	11957	1	0	0
T7	2892	6	0	0
T8	23355	61	0	0
T9	319976	369	0	0
T10	22503	58	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	20685	0	0
T1	5824	8	0	0
T2	29160	102	0	0
T3	4588	6	0	0
T4	17506	45	0	0
T5	4462	6	0	0
T6	11957	1	0	0
T7	2892	6	0	0
T8	23355	61	0	0
T9	319976	369	0	0
T10	22503	58	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	20685	0	0
T1	5085	8	0	0
T2	26110	102	0	0
T3	4250	6	0	0
T4	13560	45	0	0
T5	4076	6	0	0
T6	11939	1	0	0
T7	2751	6	0	0
T8	18943	61	0	0
T9	288237	369	0	0
T10	17247	58	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	20685	0	0
T1	5085	8	0	0
T2	26110	102	0	0
T3	4250	6	0	0
T4	13560	45	0	0
T5	4076	6	0	0
T6	11939	1	0	0
T7	2751	6	0	0
T8	18943	61	0	0
T9	288237	369	0	0
T10	17247	58	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	20685	0	0
T1	5085	8	0	0
T2	26110	102	0	0
T3	4250	6	0	0
T4	13560	45	0	0
T5	4076	6	0	0
T6	11939	1	0	0
T7	2751	6	0	0
T8	18943	61	0	0
T9	288237	369	0	0
T10	17247	58	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10354890	20685	0	0
T1	5085	8	0	0
T2	26110	102	0	0
T3	4250	6	0	0
T4	13560	45	0	0
T5	4076	6	0	0
T6	11939	1	0	0
T7	2751	6	0	0
T8	18943	61	0	0
T9	288237	369	0	0
T10	17247	58	0	0