Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	11729989	13557	0	0
gen_assertions[0].RstEnOn_A	11729989	997	0	0
gen_assertions[0].RstNOff_A	11729989	13557	0	0
gen_assertions[0].RstNOn_A	11729989	997	0	0
gen_assertions[1].RstEnOff_A	46920200	12348	0	0
gen_assertions[1].RstEnOn_A	46920200	963	0	0
gen_assertions[1].RstNOff_A	46920200	12348	0	0
gen_assertions[1].RstNOn_A	46920200	963	0	0
gen_assertions[2].RstEnOff_A	23460933	12374	0	0
gen_assertions[2].RstEnOn_A	23460933	920	0	0
gen_assertions[2].RstNOff_A	23460933	12374	0	0
gen_assertions[2].RstNOn_A	23460933	920	0	0
gen_assertions[3].RstEnOff_A	23460701	12439	0	0
gen_assertions[3].RstEnOn_A	23460701	978	0	0
gen_assertions[3].RstNOff_A	23460701	12439	0	0
gen_assertions[3].RstNOn_A	23460701	978	0	0
gen_assertions[4].RstEnOff_A	1482077	20327	0	0
gen_assertions[4].RstEnOn_A	1482077	1054	0	0
gen_assertions[4].RstNOff_A	1482077	20327	0	0
gen_assertions[4].RstNOn_A	1482077	1054	0	0
gen_assertions[5].RstEnOff_A	11729989	13810	0	0
gen_assertions[5].RstEnOn_A	11729989	1103	0	0
gen_assertions[5].RstNOff_A	11729989	13810	0	0
gen_assertions[5].RstNOn_A	11729989	1103	0	0
gen_assertions[6].RstEnOff_A	11729989	13833	0	0
gen_assertions[6].RstEnOn_A	11729989	1121	0	0
gen_assertions[6].RstNOff_A	11729989	13833	0	0
gen_assertions[6].RstNOn_A	11729989	1121	0	0
gen_assertions[7].RstEnOff_A	11729989	13867	0	0
gen_assertions[7].RstEnOn_A	11729989	1162	0	0
gen_assertions[7].RstNOff_A	11729989	13867	0	0
gen_assertions[7].RstNOn_A	11729989	1162	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	13557	0	0
T2	29160	75	0	0
T3	4588	4	0	0
T4	17506	30	0	0
T5	4462	4	0	0
T6	11957	7	0	0
T7	2892	5	0	0
T8	23355	39	0	0
T9	319976	277	0	0
T10	22503	38	0	0
T11	3211	2	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	997	0	0
T6	11957	7	0	0
T7	2892	1	0	0
T8	23355	0	0	0
T9	319976	36	0	0
T10	22503	0	0	0
T11	3211	2	0	0
T12	3423	0	0	0
T13	2640	0	0	0
T28	0	4	0	0
T30	0	1	0	0
T51	8884	10	0	0
T68	0	2	0	0
T75	5507	2	0	0
T76	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	13557	0	0
T2	29160	75	0	0
T3	4588	4	0	0
T4	17506	30	0	0
T5	4462	4	0	0
T6	11957	7	0	0
T7	2892	5	0	0
T8	23355	39	0	0
T9	319976	277	0	0
T10	22503	38	0	0
T11	3211	2	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	997	0	0
T6	11957	7	0	0
T7	2892	1	0	0
T8	23355	0	0	0
T9	319976	36	0	0
T10	22503	0	0	0
T11	3211	2	0	0
T12	3423	0	0	0
T13	2640	0	0	0
T28	0	4	0	0
T30	0	1	0	0
T51	8884	10	0	0
T68	0	2	0	0
T75	5507	2	0	0
T76	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46920200	12348	0	0
T2	116679	72	0	0
T3	18347	4	0	0
T4	70024	26	0	0
T5	17852	4	0	0
T6	47833	7	0	0
T7	11569	4	0	0
T8	93432	37	0	0
T9	127980	249	0	0
T10	90010	34	0	0
T11	12846	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46920200	963	0	0
T6	47833	7	0	0
T7	11569	0	0	0
T8	93432	0	0	0
T9	127980	34	0	0
T10	90010	0	0	0
T11	12846	3	0	0
T12	13705	0	0	0
T13	10566	0	0	0
T51	35545	7	0	0
T68	0	2	0	0
T69	0	8	0	0
T70	0	7	0	0
T73	0	1	0	0
T75	22028	0	0	0
T76	0	6	0	0
T77	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46920200	12348	0	0
T2	116679	72	0	0
T3	18347	4	0	0
T4	70024	26	0	0
T5	17852	4	0	0
T6	47833	7	0	0
T7	11569	4	0	0
T8	93432	37	0	0
T9	127980	249	0	0
T10	90010	34	0	0
T11	12846	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46920200	963	0	0
T6	47833	7	0	0
T7	11569	0	0	0
T8	93432	0	0	0
T9	127980	34	0	0
T10	90010	0	0	0
T11	12846	3	0	0
T12	13705	0	0	0
T13	10566	0	0	0
T51	35545	7	0	0
T68	0	2	0	0
T69	0	8	0	0
T70	0	7	0	0
T73	0	1	0	0
T75	22028	0	0	0
T76	0	6	0	0
T77	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460933	12374	0	0
T2	58338	72	0	0
T3	9174	4	0	0
T4	35018	26	0	0
T5	8928	4	0	0
T6	23917	8	0	0
T7	5784	4	0	0
T8	46727	37	0	0
T9	639935	247	0	0
T10	45011	34	0	0
T11	6422	5	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460933	920	0	0
T6	23917	8	0	0
T7	5784	0	0	0
T8	46727	0	0	0
T9	639935	32	0	0
T10	45011	0	0	0
T11	6422	5	0	0
T12	6851	0	0	0
T13	5280	0	0	0
T51	17772	10	0	0
T68	0	4	0	0
T69	0	9	0	0
T70	0	4	0	0
T72	0	1	0	0
T75	11014	0	0	0
T76	0	7	0	0
T77	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460933	12374	0	0
T2	58338	72	0	0
T3	9174	4	0	0
T4	35018	26	0	0
T5	8928	4	0	0
T6	23917	8	0	0
T7	5784	4	0	0
T8	46727	37	0	0
T9	639935	247	0	0
T10	45011	34	0	0
T11	6422	5	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460933	920	0	0
T6	23917	8	0	0
T7	5784	0	0	0
T8	46727	0	0	0
T9	639935	32	0	0
T10	45011	0	0	0
T11	6422	5	0	0
T12	6851	0	0	0
T13	5280	0	0	0
T51	17772	10	0	0
T68	0	4	0	0
T69	0	9	0	0
T70	0	4	0	0
T72	0	1	0	0
T75	11014	0	0	0
T76	0	7	0	0
T77	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460701	12439	0	0
T2	58322	72	0	0
T3	9175	5	0	0
T4	35024	26	0	0
T5	8925	4	0	0
T6	23917	7	0	0
T7	5784	5	0	0
T8	46723	37	0	0
T9	639921	248	0	0
T10	45015	34	0	0
T11	6422	7	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460701	978	0	0
T3	9175	1	0	0
T4	35024	0	0	0
T5	8925	0	0	0
T6	23917	7	0	0
T7	5784	1	0	0
T8	46723	0	0	0
T9	639921	33	0	0
T10	45015	0	0	0
T11	6422	7	0	0
T12	6850	0	0	0
T13	0	1	0	0
T51	0	11	0	0
T68	0	5	0	0
T69	0	6	0	0
T76	0	8	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460701	12439	0	0
T2	58322	72	0	0
T3	9175	5	0	0
T4	35024	26	0	0
T5	8925	4	0	0
T6	23917	7	0	0
T7	5784	5	0	0
T8	46723	37	0	0
T9	639921	248	0	0
T10	45015	34	0	0
T11	6422	7	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23460701	978	0	0
T3	9175	1	0	0
T4	35024	0	0	0
T5	8925	0	0	0
T6	23917	7	0	0
T7	5784	1	0	0
T8	46723	0	0	0
T9	639921	33	0	0
T10	45015	0	0	0
T11	6422	7	0	0
T12	6850	0	0	0
T13	0	1	0	0
T51	0	11	0	0
T68	0	5	0	0
T69	0	6	0	0
T76	0	8	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482077	20327	0	0
T1	730	3	0	0
T2	3660	76	0	0
T3	572	6	0	0
T4	2224	45	0	0
T5	556	6	0	0
T6	1492	10	0	0
T7	361	6	0	0
T8	2991	61	0	0
T9	40393	399	0	0
T10	2910	58	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482077	1054	0	0
T6	1492	9	0	0
T7	361	0	0	0
T8	2991	0	0	0
T9	40393	33	0	0
T10	2910	0	0	0
T11	399	6	0	0
T12	427	0	0	0
T13	330	1	0	0
T51	1110	14	0	0
T68	0	6	0	0
T69	0	13	0	0
T70	0	2	0	0
T75	688	0	0	0
T76	0	7	0	0
T78	0	4	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482077	20327	0	0
T1	730	3	0	0
T2	3660	76	0	0
T3	572	6	0	0
T4	2224	45	0	0
T5	556	6	0	0
T6	1492	10	0	0
T7	361	6	0	0
T8	2991	61	0	0
T9	40393	399	0	0
T10	2910	58	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1482077	1054	0	0
T6	1492	9	0	0
T7	361	0	0	0
T8	2991	0	0	0
T9	40393	33	0	0
T10	2910	0	0	0
T11	399	6	0	0
T12	427	0	0	0
T13	330	1	0	0
T51	1110	14	0	0
T68	0	6	0	0
T69	0	13	0	0
T70	0	2	0	0
T75	688	0	0	0
T76	0	7	0	0
T78	0	4	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	13810	0	0
T2	29160	75	0	0
T3	4588	4	0	0
T4	17506	30	0	0
T5	4462	4	0	0
T6	11957	12	0	0
T7	2892	4	0	0
T8	23355	39	0	0
T9	319976	271	0	0
T10	22503	38	0	0
T11	3211	9	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	1103	0	0
T6	11957	12	0	0
T7	2892	0	0	0
T8	23355	0	0	0
T9	319976	30	0	0
T10	22503	0	0	0
T11	3211	9	0	0
T12	3423	0	0	0
T13	2640	0	0	0
T51	8884	13	0	0
T68	0	6	0	0
T69	0	11	0	0
T70	0	7	0	0
T72	0	1	0	0
T75	5507	0	0	0
T76	0	5	0	0
T78	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	13810	0	0
T2	29160	75	0	0
T3	4588	4	0	0
T4	17506	30	0	0
T5	4462	4	0	0
T6	11957	12	0	0
T7	2892	4	0	0
T8	23355	39	0	0
T9	319976	271	0	0
T10	22503	38	0	0
T11	3211	9	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	1103	0	0
T6	11957	12	0	0
T7	2892	0	0	0
T8	23355	0	0	0
T9	319976	30	0	0
T10	22503	0	0	0
T11	3211	9	0	0
T12	3423	0	0	0
T13	2640	0	0	0
T51	8884	13	0	0
T68	0	6	0	0
T69	0	11	0	0
T70	0	7	0	0
T72	0	1	0	0
T75	5507	0	0	0
T76	0	5	0	0
T78	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	13833	0	0
T2	29160	75	0	0
T3	4588	4	0	0
T4	17506	30	0	0
T5	4462	4	0	0
T6	11957	11	0	0
T7	2892	4	0	0
T8	23355	39	0	0
T9	319976	273	0	0
T10	22503	38	0	0
T11	3211	8	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	1121	0	0
T6	11957	11	0	0
T7	2892	0	0	0
T8	23355	0	0	0
T9	319976	32	0	0
T10	22503	0	0	0
T11	3211	8	0	0
T12	3423	0	0	0
T13	2640	0	0	0
T30	0	1	0	0
T51	8884	14	0	0
T68	0	8	0	0
T69	0	15	0	0
T70	0	8	0	0
T72	0	1	0	0
T75	5507	0	0	0
T76	0	9	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	13833	0	0
T2	29160	75	0	0
T3	4588	4	0	0
T4	17506	30	0	0
T5	4462	4	0	0
T6	11957	11	0	0
T7	2892	4	0	0
T8	23355	39	0	0
T9	319976	273	0	0
T10	22503	38	0	0
T11	3211	8	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	1121	0	0
T6	11957	11	0	0
T7	2892	0	0	0
T8	23355	0	0	0
T9	319976	32	0	0
T10	22503	0	0	0
T11	3211	8	0	0
T12	3423	0	0	0
T13	2640	0	0	0
T30	0	1	0	0
T51	8884	14	0	0
T68	0	8	0	0
T69	0	15	0	0
T70	0	8	0	0
T72	0	1	0	0
T75	5507	0	0	0
T76	0	9	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	13867	0	0
T2	29160	75	0	0
T3	4588	4	0	0
T4	17506	30	0	0
T5	4462	4	0	0
T6	11957	15	0	0
T7	2892	4	0	0
T8	23355	39	0	0
T9	319976	273	0	0
T10	22503	38	0	0
T11	3211	10	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	1162	0	0
T6	11957	15	0	0
T7	2892	0	0	0
T8	23355	0	0	0
T9	319976	32	0	0
T10	22503	0	0	0
T11	3211	10	0	0
T12	3423	0	0	0
T13	2640	0	0	0
T30	0	1	0	0
T51	8884	16	0	0
T68	0	9	0	0
T69	0	15	0	0
T70	0	6	0	0
T72	0	1	0	0
T75	5507	0	0	0
T76	0	5	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	13867	0	0
T2	29160	75	0	0
T3	4588	4	0	0
T4	17506	30	0	0
T5	4462	4	0	0
T6	11957	15	0	0
T7	2892	4	0	0
T8	23355	39	0	0
T9	319976	273	0	0
T10	22503	38	0	0
T11	3211	10	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11729989	1162	0	0
T6	11957	15	0	0
T7	2892	0	0	0
T8	23355	0	0	0
T9	319976	32	0	0
T10	22503	0	0	0
T11	3211	10	0	0
T12	3423	0	0	0
T13	2640	0	0	0
T30	0	1	0	0
T51	8884	16	0	0
T68	0	9	0	0
T69	0	15	0	0
T70	0	6	0	0
T72	0	1	0	0
T75	5507	0	0	0
T76	0	5	0	0