Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11126889	8866	0	0
alert_regwen_rd_A	11126889	4792	0	0
cpu_regwen_rd_A	11126889	4877	0	0
sw_rst_ctrl_n_0_rd_A	11126889	8648	0	0
sw_rst_ctrl_n_1_rd_A	11126889	8520	0	0
sw_rst_ctrl_n_2_rd_A	11126889	8247	0	0
sw_rst_ctrl_n_3_rd_A	11126889	8426	0	0
sw_rst_ctrl_n_4_rd_A	11126889	8605	0	0
sw_rst_ctrl_n_5_rd_A	11126889	8550	0	0
sw_rst_ctrl_n_6_rd_A	11126889	8045	0	0
sw_rst_ctrl_n_7_rd_A	11126889	8402	0	0
sw_rst_regwen_0_rd_A	11126889	5190	0	0
sw_rst_regwen_1_rd_A	11126889	5174	0	0
sw_rst_regwen_2_rd_A	11126889	5270	0	0
sw_rst_regwen_3_rd_A	11126889	5254	0	0
sw_rst_regwen_4_rd_A	11126889	5281	0	0
sw_rst_regwen_5_rd_A	11126889	5200	0	0
sw_rst_regwen_6_rd_A	11126889	5199	0	0
sw_rst_regwen_7_rd_A	11126889	5431	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	8866	0	0
T52	11915	2	0	0
T56	4029	118	0	0
T57	7112	279	0	0
T58	2298	35	0	0
T64	11161	2	0	0
T65	2716	41	0	0
T79	2575	153	0	0
T80	9853	385	0	0
T81	2556	5	0	0
T106	18114	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	4792	0	0
T9	288237	385	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T45	5072	0	0	0
T51	8819	0	0	0
T62	1259	0	0	0
T63	1553	0	0	0
T75	4481	0	0	0
T88	0	56	0	0
T92	0	111	0	0
T93	0	126	0	0
T116	0	80	0	0
T117	0	47	0	0
T118	0	88	0	0
T119	0	501	0	0
T120	0	326	0	0
T121	0	26	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	4877	0	0
T9	288237	475	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T45	5072	0	0	0
T51	8819	0	0	0
T62	1259	0	0	0
T63	1553	0	0	0
T75	4481	0	0	0
T88	0	49	0	0
T92	0	125	0	0
T93	0	120	0	0
T116	0	64	0	0
T117	0	18	0	0
T118	0	54	0	0
T119	0	503	0	0
T120	0	371	0	0
T121	0	18	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	8648	0	0
T6	11939	188	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	883	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T28	0	34	0	0
T51	8819	0	0	0
T69	0	114	0	0
T75	4481	54	0	0
T88	0	51	0	0
T122	0	102	0	0
T123	0	13	0	0
T124	0	70	0	0
T125	0	42	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	8520	0	0
T6	11939	207	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	890	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T28	0	53	0	0
T51	8819	0	0	0
T69	0	79	0	0
T75	4481	45	0	0
T88	0	77	0	0
T122	0	104	0	0
T123	0	13	0	0
T124	0	29	0	0
T125	0	58	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	8247	0	0
T6	11939	182	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	842	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T28	0	41	0	0
T51	8819	0	0	0
T69	0	83	0	0
T75	4481	35	0	0
T88	0	74	0	0
T122	0	94	0	0
T123	0	4	0	0
T124	0	35	0	0
T125	0	64	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	8426	0	0
T6	11939	153	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	826	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T28	0	48	0	0
T51	8819	0	0	0
T69	0	121	0	0
T75	4481	52	0	0
T88	0	61	0	0
T122	0	93	0	0
T123	0	11	0	0
T124	0	47	0	0
T125	0	49	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	8605	0	0
T6	11939	180	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	898	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T28	0	47	0	0
T51	8819	0	0	0
T69	0	151	0	0
T75	4481	52	0	0
T88	0	69	0	0
T122	0	97	0	0
T123	0	8	0	0
T124	0	56	0	0
T125	0	87	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	8550	0	0
T6	11939	193	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	890	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T28	0	45	0	0
T51	8819	0	0	0
T69	0	145	0	0
T75	4481	49	0	0
T88	0	64	0	0
T122	0	134	0	0
T123	0	13	0	0
T124	0	56	0	0
T125	0	55	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	8045	0	0
T6	11939	177	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	844	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T28	0	39	0	0
T51	8819	0	0	0
T69	0	92	0	0
T75	4481	38	0	0
T88	0	66	0	0
T122	0	88	0	0
T123	0	22	0	0
T124	0	53	0	0
T125	0	61	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	8402	0	0
T6	11939	227	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	827	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T28	0	71	0	0
T51	8819	0	0	0
T69	0	109	0	0
T75	4481	40	0	0
T88	0	42	0	0
T122	0	90	0	0
T123	0	12	0	0
T124	0	62	0	0
T125	0	59	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	5190	0	0
T6	11939	24	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	455	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T51	8819	0	0	0
T69	0	19	0	0
T75	4481	0	0	0
T88	0	67	0	0
T92	0	140	0	0
T93	0	126	0	0
T116	0	69	0	0
T122	0	13	0	0
T123	0	8	0	0
T126	0	15	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	5174	0	0
T6	11939	42	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	390	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T51	8819	0	0	0
T69	0	16	0	0
T75	4481	0	0	0
T88	0	65	0	0
T92	0	112	0	0
T93	0	150	0	0
T116	0	51	0	0
T122	0	29	0	0
T123	0	6	0	0
T126	0	5	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	5270	0	0
T6	11939	46	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	365	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T51	8819	0	0	0
T69	0	13	0	0
T75	4481	0	0	0
T88	0	70	0	0
T92	0	130	0	0
T93	0	158	0	0
T116	0	73	0	0
T122	0	5	0	0
T123	0	11	0	0
T126	0	7	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	5254	0	0
T6	11939	25	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	447	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T51	8819	0	0	0
T69	0	19	0	0
T75	4481	0	0	0
T88	0	48	0	0
T92	0	122	0	0
T93	0	129	0	0
T116	0	47	0	0
T122	0	12	0	0
T123	0	6	0	0
T126	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	5281	0	0
T6	11939	36	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	433	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T51	8819	0	0	0
T69	0	26	0	0
T75	4481	0	0	0
T88	0	55	0	0
T92	0	118	0	0
T93	0	123	0	0
T116	0	71	0	0
T122	0	12	0	0
T123	0	6	0	0
T126	0	1	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	5200	0	0
T6	11939	35	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	415	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T51	8819	0	0	0
T69	0	21	0	0
T75	4481	0	0	0
T88	0	79	0	0
T92	0	146	0	0
T93	0	152	0	0
T116	0	67	0	0
T122	0	13	0	0
T123	0	16	0	0
T126	0	10	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	5199	0	0
T6	11939	26	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	459	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T51	8819	0	0	0
T69	0	12	0	0
T75	4481	0	0	0
T88	0	74	0	0
T92	0	101	0	0
T93	0	113	0	0
T116	0	47	0	0
T122	0	26	0	0
T123	0	13	0	0
T126	0	10	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11126889	5431	0	0
T6	11939	31	0	0
T7	2751	0	0	0
T8	18943	0	0	0
T9	288237	414	0	0
T10	17247	0	0	0
T11	3168	0	0	0
T12	3182	0	0	0
T13	2400	0	0	0
T51	8819	0	0	0
T69	0	11	0	0
T75	4481	0	0	0
T88	0	66	0	0
T92	0	136	0	0
T93	0	112	0	0
T116	0	73	0	0
T122	0	29	0	0
T123	0	5	0	0
T126	0	11	0	0