Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	590953	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

356976

1

T1

246

T2

145

T3

1076

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	504512	1			T1	355		T2	186		T3	1500
values[0x0]	221016	1			T1	162		T2	103		T3	823
values[0x1]	222401	1			T1	147		T2	90		T3	877

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	496178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

451751

1

T1

312

T2

181

T3

1408

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3632	1			T1	3		T2	4		T3	5
valid_sources[0x01]	4334	1			T1	3		T3	12		T8	5
valid_sources[0x02]	3568	1			T1	1		T3	13		T8	3
valid_sources[0x03]	3174	1			T3	10		T8	2		T9	1
valid_sources[0x04]	3289	1			T1	4		T3	14		T8	3
valid_sources[0x05]	3176	1			T1	2		T3	12		T9	7
valid_sources[0x06]	3110	1			T1	3		T2	1		T3	12
valid_sources[0x07]	3700	1			T1	2		T2	6		T3	19
valid_sources[0x08]	3496	1			T1	2		T2	1		T3	19
valid_sources[0x09]	3995	1			T1	3		T2	3		T3	18
valid_sources[0x0a]	3242	1			T1	1		T3	26		T4	2
valid_sources[0x0b]	4237	1			T1	6		T3	9		T5	212
valid_sources[0x0c]	3091	1			T1	3		T2	2		T3	12
valid_sources[0x0d]	3510	1			T1	2		T2	4		T3	16
valid_sources[0x0e]	3439	1			T1	1		T2	4		T3	10
valid_sources[0x0f]	3003	1			T1	4		T2	7		T3	17
valid_sources[0x10]	3764	1			T1	3		T3	8		T8	1
valid_sources[0x11]	3494	1			T1	1		T2	1		T3	8
valid_sources[0x12]	3455	1			T1	3		T2	1		T3	21
valid_sources[0x13]	4731	1			T1	2		T2	1		T3	4
valid_sources[0x14]	3026	1			T1	4		T2	1		T3	6
valid_sources[0x15]	3729	1			T1	4		T2	1		T3	16
valid_sources[0x16]	3459	1			T1	2		T2	2		T3	13
valid_sources[0x17]	8326	1			T2	2		T3	13		T8	1
valid_sources[0x18]	3468	1			T1	2		T3	17		T8	3
valid_sources[0x19]	5801	1			T1	9		T3	13		T8	5
valid_sources[0x1a]	3321	1			T1	4		T3	15		T8	2
valid_sources[0x1b]	6655	1			T3	3		T4	2		T9	6
valid_sources[0x1c]	3271	1			T1	3		T2	3		T3	11
valid_sources[0x1d]	3196	1			T1	2		T2	2		T3	8
valid_sources[0x1e]	3487	1			T1	3		T2	1		T3	15
valid_sources[0x1f]	3546	1			T1	4		T2	1		T3	8
valid_sources[0x20]	3257	1			T2	1		T3	13		T4	1
valid_sources[0x21]	3340	1			T1	6		T3	14		T9	2
valid_sources[0x22]	3522	1			T1	1		T2	1		T3	20
valid_sources[0x23]	3234	1			T1	4		T3	17		T4	1
valid_sources[0x24]	3578	1			T1	5		T3	10		T8	5
valid_sources[0x25]	3386	1			T1	8		T2	4		T3	13
valid_sources[0x26]	3959	1			T1	2		T2	2		T3	10
valid_sources[0x27]	3403	1			T1	2		T2	1		T3	6
valid_sources[0x28]	3370	1			T1	1		T2	1		T3	23
valid_sources[0x29]	3175	1			T1	4		T2	7		T3	17
valid_sources[0x2a]	3527	1			T1	5		T2	2		T3	10
valid_sources[0x2b]	3967	1			T1	5		T3	7		T4	7
valid_sources[0x2c]	3317	1			T1	3		T3	13		T4	1
valid_sources[0x2d]	3505	1			T1	4		T2	1		T3	8
valid_sources[0x2e]	3687	1			T1	2		T2	2		T3	9
valid_sources[0x2f]	4218	1			T1	2		T2	1		T3	13
valid_sources[0x30]	3165	1			T1	3		T2	6		T3	20
valid_sources[0x31]	3153	1			T1	1		T3	10		T4	10
valid_sources[0x32]	5358	1			T1	6		T3	24		T8	3
valid_sources[0x33]	3693	1			T1	5		T2	1		T3	22
valid_sources[0x34]	4319	1			T1	1		T3	15		T8	4
valid_sources[0x35]	3026	1			T1	3		T3	8		T4	6
valid_sources[0x36]	3612	1			T1	6		T3	6		T4	3
valid_sources[0x37]	3020	1			T1	3		T3	10		T8	1
valid_sources[0x38]	3441	1			T1	1		T2	1		T3	20
valid_sources[0x39]	3023	1			T1	1		T2	1		T3	7
valid_sources[0x3a]	3696	1			T1	4		T3	9		T8	4
valid_sources[0x3b]	3312	1			T2	1		T3	17		T8	1
valid_sources[0x3c]	3066	1			T1	2		T3	6		T8	3
valid_sources[0x3d]	2875	1			T1	3		T2	2		T3	10
valid_sources[0x3e]	3599	1			T1	1		T2	6		T3	14
valid_sources[0x3f]	3195	1			T2	1		T3	9		T9	3
valid_sources[0x40]	3787	1			T1	1		T2	1		T3	8
valid_sources[0x41]	2896	1			T1	4		T2	1		T3	5
valid_sources[0x42]	3060	1			T1	2		T2	2		T3	23
valid_sources[0x43]	4468	1			T1	4		T2	1		T3	16
valid_sources[0x44]	3547	1			T1	5		T3	13		T8	1
valid_sources[0x45]	3451	1			T1	3		T2	2		T3	12
valid_sources[0x46]	3203	1			T1	2		T2	1		T3	7
valid_sources[0x47]	3622	1			T1	2		T3	6		T8	1
valid_sources[0x48]	3713	1			T1	2		T2	4		T3	11
valid_sources[0x49]	3052	1			T1	3		T3	8		T8	2
valid_sources[0x4a]	3702	1			T1	3		T2	2		T3	17
valid_sources[0x4b]	3203	1			T1	1		T2	1		T3	12
valid_sources[0x4c]	2823	1			T1	5		T3	22		T4	6
valid_sources[0x4d]	3274	1			T1	1		T2	1		T3	14
valid_sources[0x4e]	3036	1			T1	3		T2	1		T3	11
valid_sources[0x4f]	3153	1			T1	1		T2	2		T3	17
valid_sources[0x50]	3785	1			T1	2		T2	3		T3	9
valid_sources[0x51]	3091	1			T1	5		T3	14		T8	3
valid_sources[0x52]	3337	1			T1	5		T2	3		T3	9
valid_sources[0x53]	2998	1			T1	4		T2	2		T3	21
valid_sources[0x54]	3389	1			T1	7		T2	2		T3	31
valid_sources[0x55]	3864	1			T1	3		T2	1		T3	11
valid_sources[0x56]	3661	1			T1	1		T3	17		T8	3
valid_sources[0x57]	4488	1			T1	2		T3	8		T4	1
valid_sources[0x58]	5301	1			T1	5		T3	8		T8	4
valid_sources[0x59]	4652	1			T2	1		T3	6		T8	5
valid_sources[0x5a]	3457	1			T3	11		T8	2		T9	6
valid_sources[0x5b]	3424	1			T1	1		T3	8		T8	3
valid_sources[0x5c]	3651	1			T1	9		T2	2		T3	8
valid_sources[0x5d]	6093	1			T2	1		T3	8		T8	3
valid_sources[0x5e]	4458	1			T1	1		T2	4		T3	14
valid_sources[0x5f]	3401	1			T1	4		T2	1		T3	8
valid_sources[0x60]	2998	1			T1	4		T2	5		T3	10
valid_sources[0x61]	3510	1			T1	1		T3	7		T8	5
valid_sources[0x62]	3538	1			T1	3		T2	2		T3	22
valid_sources[0x63]	3313	1			T2	1		T3	5		T8	2
valid_sources[0x64]	3071	1			T1	1		T2	5		T3	18
valid_sources[0x65]	4307	1			T1	6		T2	3		T3	11
valid_sources[0x66]	3073	1			T1	2		T3	7		T8	1
valid_sources[0x67]	4238	1			T1	3		T2	1		T3	15
valid_sources[0x68]	3318	1			T1	5		T2	4		T3	12
valid_sources[0x69]	2871	1			T1	1		T2	1		T3	11
valid_sources[0x6a]	3097	1			T1	2		T2	2		T3	4
valid_sources[0x6b]	3201	1			T1	3		T2	1		T3	10
valid_sources[0x6c]	3116	1			T1	2		T2	2		T3	10
valid_sources[0x6d]	4509	1			T1	5		T2	1		T3	18
valid_sources[0x6e]	2984	1			T1	3		T2	1		T3	11
valid_sources[0x6f]	2816	1			T1	3		T2	1		T3	17
valid_sources[0x70]	4715	1			T1	2		T3	9		T8	2
valid_sources[0x71]	3698	1			T1	4		T2	1		T3	12
valid_sources[0x72]	3809	1			T1	1		T2	1		T3	11
valid_sources[0x73]	3479	1			T1	2		T3	8		T8	4
valid_sources[0x74]	3333	1			T1	2		T2	2		T3	5
valid_sources[0x75]	3317	1			T1	2		T2	1		T3	17
valid_sources[0x76]	3859	1			T3	9		T8	6		T33	1
valid_sources[0x77]	3841	1			T1	1		T2	3		T3	7
valid_sources[0x78]	3364	1			T1	2		T2	5		T3	3
valid_sources[0x79]	3762	1			T3	13		T8	3		T9	1
valid_sources[0x7a]	6603	1			T1	3		T2	3		T3	15
valid_sources[0x7b]	4217	1			T1	3		T3	10		T8	1
valid_sources[0x7c]	3266	1			T1	1		T2	1		T3	15
valid_sources[0x7d]	3908	1			T1	1		T2	2		T3	15
valid_sources[0x7e]	4040	1			T1	2		T3	19		T8	2
valid_sources[0x7f]	3105	1			T2	1		T3	13		T8	5
valid_sources[0x80]	3598	1			T1	3		T2	2		T3	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

237005

1

T1

177

T2

92

T3

675

values[0x0]

all_enables

biggest_size

77910

1

T1

48

T2

36

T3

271

values[0x1]

all_enables

biggest_size

42061

1

T1

21

T2

17

T3

130