Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T4,T12,T32
1	0	Covered	T32,T45,T46

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53472239	8588	0	0
CascadeEffAonToRstPorAboveRise_A	53472239	8588	0	0
CascadeEffAonToRstPorIoAboveFall_A	51332150	8588	0	0
CascadeEffAonToRstPorIoAboveRise_A	51332150	8588	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25666601	8588	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25666601	8588	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12832986	8588	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12832986	8588	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25666877	8588	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25666877	8588	0	0
CascadeLcToLcAboveFall_A	53472239	21076	0	0
CascadeLcToLcAboveRise_A	53472239	21076	0	0
CascadeLcToLcAonAboveFall_A	1619488	21076	0	0
CascadeLcToLcAonAboveRise_A	1619488	21076	0	0
CascadeLcToLcShadowedAboveFall_A	53472239	21076	0	0
CascadeLcToLcShadowedAboveRise_A	53472239	21076	0	0
CascadePorToAonAboveFall_A	1619488	6885	0	0
CascadeSysToSysAboveFall_A	53472239	21076	0	0
CascadeSysToSysAboveRise_A	53472239	21076	0	0
ScanRstToAonRise_A	1619488	227	0	0
StablePorToAonRise_A	1619488	8588	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11399153	21076	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11399153	21076	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11399153	21076	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11399153	21076	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12832986	21076	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12832986	21076	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11399153	21076	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11399153	21076	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11399153	21076	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11399153	21076	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53472239	8588	0	0
T1	11972	1	0	0
T2	12886	2	0	0
T3	217820	27	0	0
T4	16153	2	0	0
T5	15130	2	0	0
T6	21734	1	0	0
T7	24449	8	0	0
T8	12572	1	0	0
T9	13290	1	0	0
T10	218940	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53472239	8588	0	0
T1	11972	1	0	0
T2	12886	2	0	0
T3	217820	27	0	0
T4	16153	2	0	0
T5	15130	2	0	0
T6	21734	1	0	0
T7	24449	8	0	0
T8	12572	1	0	0
T9	13290	1	0	0
T10	218940	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51332150	8588	0	0
T1	11492	1	0	0
T2	12376	2	0	0
T3	209020	27	0	0
T4	15503	2	0	0
T5	14531	2	0	0
T6	20864	1	0	0
T7	23449	8	0	0
T8	12069	1	0	0
T9	12758	1	0	0
T10	210184	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51332150	8588	0	0
T1	11492	1	0	0
T2	12376	2	0	0
T3	209020	27	0	0
T4	15503	2	0	0
T5	14531	2	0	0
T6	20864	1	0	0
T7	23449	8	0	0
T8	12069	1	0	0
T9	12758	1	0	0
T10	210184	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666601	8588	0	0
T1	5746	1	0	0
T2	6185	2	0	0
T3	104552	27	0	0
T4	7752	2	0	0
T5	7262	2	0	0
T6	10432	1	0	0
T7	11728	8	0	0
T8	6034	1	0	0
T9	6379	1	0	0
T10	105082	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666601	8588	0	0
T1	5746	1	0	0
T2	6185	2	0	0
T3	104552	27	0	0
T4	7752	2	0	0
T5	7262	2	0	0
T6	10432	1	0	0
T7	11728	8	0	0
T8	6034	1	0	0
T9	6379	1	0	0
T10	105082	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	8588	0	0
T1	2872	1	0	0
T2	3092	2	0	0
T3	52279	27	0	0
T4	3876	2	0	0
T5	3631	2	0	0
T6	5216	1	0	0
T7	5866	8	0	0
T8	3016	1	0	0
T9	3189	1	0	0
T10	52546	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	8588	0	0
T1	2872	1	0	0
T2	3092	2	0	0
T3	52279	27	0	0
T4	3876	2	0	0
T5	3631	2	0	0
T6	5216	1	0	0
T7	5866	8	0	0
T8	3016	1	0	0
T9	3189	1	0	0
T10	52546	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666877	8588	0	0
T1	5746	1	0	0
T2	6184	2	0	0
T3	104547	27	0	0
T4	7752	2	0	0
T5	7263	2	0	0
T6	10432	1	0	0
T7	11732	8	0	0
T8	6034	1	0	0
T9	6378	1	0	0
T10	105103	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666877	8588	0	0
T1	5746	1	0	0
T2	6184	2	0	0
T3	104547	27	0	0
T4	7752	2	0	0
T5	7263	2	0	0
T6	10432	1	0	0
T7	11732	8	0	0
T8	6034	1	0	0
T9	6378	1	0	0
T10	105103	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53472239	21076	0	0
T1	11972	1	0	0
T2	12886	6	0	0
T3	217820	102	0	0
T4	16153	6	0	0
T5	15130	6	0	0
T6	21734	15	0	0
T7	24449	8	0	0
T8	12572	1	0	0
T9	13290	1	0	0
T10	218940	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53472239	21076	0	0
T1	11972	1	0	0
T2	12886	6	0	0
T3	217820	102	0	0
T4	16153	6	0	0
T5	15130	6	0	0
T6	21734	15	0	0
T7	24449	8	0	0
T8	12572	1	0	0
T9	13290	1	0	0
T10	218940	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1619488	21076	0	0
T1	357	1	0	0
T2	385	6	0	0
T3	6549	102	0	0
T4	484	6	0	0
T5	452	6	0	0
T6	651	15	0	0
T7	735	8	0	0
T8	375	1	0	0
T9	397	1	0	0
T10	6583	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1619488	21076	0	0
T1	357	1	0	0
T2	385	6	0	0
T3	6549	102	0	0
T4	484	6	0	0
T5	452	6	0	0
T6	651	15	0	0
T7	735	8	0	0
T8	375	1	0	0
T9	397	1	0	0
T10	6583	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53472239	21076	0	0
T1	11972	1	0	0
T2	12886	6	0	0
T3	217820	102	0	0
T4	16153	6	0	0
T5	15130	6	0	0
T6	21734	15	0	0
T7	24449	8	0	0
T8	12572	1	0	0
T9	13290	1	0	0
T10	218940	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53472239	21076	0	0
T1	11972	1	0	0
T2	12886	6	0	0
T3	217820	102	0	0
T4	16153	6	0	0
T5	15130	6	0	0
T6	21734	15	0	0
T7	24449	8	0	0
T8	12572	1	0	0
T9	13290	1	0	0
T10	218940	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1619488	6885	0	0
T1	357	1	0	0
T2	385	1	0	0
T3	6549	27	0	0
T4	484	1	0	0
T5	452	1	0	0
T6	651	1	0	0
T7	735	8	0	0
T8	375	1	0	0
T9	397	1	0	0
T10	6583	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53472239	21076	0	0
T1	11972	1	0	0
T2	12886	6	0	0
T3	217820	102	0	0
T4	16153	6	0	0
T5	15130	6	0	0
T6	21734	15	0	0
T7	24449	8	0	0
T8	12572	1	0	0
T9	13290	1	0	0
T10	218940	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53472239	21076	0	0
T1	11972	1	0	0
T2	12886	6	0	0
T3	217820	102	0	0
T4	16153	6	0	0
T5	15130	6	0	0
T6	21734	15	0	0
T7	24449	8	0	0
T8	12572	1	0	0
T9	13290	1	0	0
T10	218940	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1619488	227	0	0
T32	5298	2	0	0
T43	731	0	0	0
T44	232	0	0	0
T45	605	0	0	0
T46	17027	3	0	0
T47	731	0	0	0
T48	197	0	0	0
T49	703	0	0	0
T55	49583	0	0	0
T56	3998	0	0	0
T80	0	8	0	0
T88	0	9	0	0
T89	0	2	0	0
T90	0	2	0	0
T93	0	3	0	0
T94	0	4	0	0
T95	0	1	0	0
T115	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1619488	8588	0	0
T1	357	1	0	0
T2	385	2	0	0
T3	6549	27	0	0
T4	484	2	0	0
T5	452	2	0	0
T6	651	1	0	0
T7	735	8	0	0
T8	375	1	0	0
T9	397	1	0	0
T10	6583	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11399153	21076	0	0
T1	2806	1	0	0
T2	2707	6	0	0
T3	48850	102	0	0
T4	3542	6	0	0
T5	3392	6	0	0
T6	4189	15	0	0
T7	5320	8	0	0
T8	2974	1	0	0
T9	3122	1	0	0
T10	49192	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11399153	21076	0	0
T1	2806	1	0	0
T2	2707	6	0	0
T3	48850	102	0	0
T4	3542	6	0	0
T5	3392	6	0	0
T6	4189	15	0	0
T7	5320	8	0	0
T8	2974	1	0	0
T9	3122	1	0	0
T10	49192	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11399153	21076	0	0
T1	2806	1	0	0
T2	2707	6	0	0
T3	48850	102	0	0
T4	3542	6	0	0
T5	3392	6	0	0
T6	4189	15	0	0
T7	5320	8	0	0
T8	2974	1	0	0
T9	3122	1	0	0
T10	49192	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11399153	21076	0	0
T1	2806	1	0	0
T2	2707	6	0	0
T3	48850	102	0	0
T4	3542	6	0	0
T5	3392	6	0	0
T6	4189	15	0	0
T7	5320	8	0	0
T8	2974	1	0	0
T9	3122	1	0	0
T10	49192	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	21076	0	0
T1	2872	1	0	0
T2	3092	6	0	0
T3	52279	102	0	0
T4	3876	6	0	0
T5	3631	6	0	0
T6	5216	15	0	0
T7	5866	8	0	0
T8	3016	1	0	0
T9	3189	1	0	0
T10	52546	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	21076	0	0
T1	2872	1	0	0
T2	3092	6	0	0
T3	52279	102	0	0
T4	3876	6	0	0
T5	3631	6	0	0
T6	5216	15	0	0
T7	5866	8	0	0
T8	3016	1	0	0
T9	3189	1	0	0
T10	52546	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11399153	21076	0	0
T1	2806	1	0	0
T2	2707	6	0	0
T3	48850	102	0	0
T4	3542	6	0	0
T5	3392	6	0	0
T6	4189	15	0	0
T7	5320	8	0	0
T8	2974	1	0	0
T9	3122	1	0	0
T10	49192	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11399153	21076	0	0
T1	2806	1	0	0
T2	2707	6	0	0
T3	48850	102	0	0
T4	3542	6	0	0
T5	3392	6	0	0
T6	4189	15	0	0
T7	5320	8	0	0
T8	2974	1	0	0
T9	3122	1	0	0
T10	49192	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11399153	21076	0	0
T1	2806	1	0	0
T2	2707	6	0	0
T3	48850	102	0	0
T4	3542	6	0	0
T5	3392	6	0	0
T6	4189	15	0	0
T7	5320	8	0	0
T8	2974	1	0	0
T9	3122	1	0	0
T10	49192	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11399153	21076	0	0
T1	2806	1	0	0
T2	2707	6	0	0
T3	48850	102	0	0
T4	3542	6	0	0
T5	3392	6	0	0
T6	4189	15	0	0
T7	5320	8	0	0
T8	2974	1	0	0
T9	3122	1	0	0
T10	49192	102	0	0