Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12832986	13354	0	0
gen_assertions[0].RstEnOn_A	12832986	1045	0	0
gen_assertions[0].RstNOff_A	12832986	13354	0	0
gen_assertions[0].RstNOn_A	12832986	1045	0	0
gen_assertions[1].RstEnOff_A	51332150	12111	0	0
gen_assertions[1].RstEnOn_A	51332150	1028	0	0
gen_assertions[1].RstNOff_A	51332150	12111	0	0
gen_assertions[1].RstNOn_A	51332150	1028	0	0
gen_assertions[2].RstEnOff_A	25666601	12138	0	0
gen_assertions[2].RstEnOn_A	25666601	1013	0	0
gen_assertions[2].RstNOff_A	25666601	12138	0	0
gen_assertions[2].RstNOn_A	25666601	1013	0	0
gen_assertions[3].RstEnOff_A	25666877	12201	0	0
gen_assertions[3].RstEnOn_A	25666877	1073	0	0
gen_assertions[3].RstNOff_A	25666877	12201	0	0
gen_assertions[3].RstNOn_A	25666877	1073	0	0
gen_assertions[4].RstEnOff_A	1619488	20985	0	0
gen_assertions[4].RstEnOn_A	1619488	1111	0	0
gen_assertions[4].RstNOff_A	1619488	20985	0	0
gen_assertions[4].RstNOn_A	1619488	1111	0	0
gen_assertions[5].RstEnOff_A	12832986	13614	0	0
gen_assertions[5].RstEnOn_A	12832986	1160	0	0
gen_assertions[5].RstNOff_A	12832986	13614	0	0
gen_assertions[5].RstNOn_A	12832986	1160	0	0
gen_assertions[6].RstEnOff_A	12832986	13688	0	0
gen_assertions[6].RstEnOn_A	12832986	1241	0	0
gen_assertions[6].RstNOff_A	12832986	13688	0	0
gen_assertions[6].RstNOn_A	12832986	1241	0	0
gen_assertions[7].RstEnOff_A	12832986	13732	0	0
gen_assertions[7].RstEnOn_A	12832986	1283	0	0
gen_assertions[7].RstNOff_A	12832986	13732	0	0
gen_assertions[7].RstNOn_A	12832986	1283	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	13354	0	0
T2	3092	4	0	0
T3	52279	75	0	0
T4	3876	4	0	0
T5	3631	4	0	0
T6	5216	14	0	0
T7	5866	0	0	0
T8	3016	2	0	0
T9	3189	2	0	0
T10	52546	75	0	0
T11	3331	9	0	0
T33	0	1	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	1045	0	0
T6	5216	5	0	0
T7	5866	0	0	0
T8	3016	2	0	0
T9	3189	2	0	0
T10	52546	0	0	0
T11	3331	1	0	0
T12	3559	0	0	0
T13	2648	0	0	0
T14	0	2	0	0
T15	5849	0	0	0
T27	0	2	0	0
T33	8799	1	0	0
T46	0	38	0	0
T49	0	1	0	0
T79	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	13354	0	0
T2	3092	4	0	0
T3	52279	75	0	0
T4	3876	4	0	0
T5	3631	4	0	0
T6	5216	14	0	0
T7	5866	0	0	0
T8	3016	2	0	0
T9	3189	2	0	0
T10	52546	75	0	0
T11	3331	9	0	0
T33	0	1	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	1045	0	0
T6	5216	5	0	0
T7	5866	0	0	0
T8	3016	2	0	0
T9	3189	2	0	0
T10	52546	0	0	0
T11	3331	1	0	0
T12	3559	0	0	0
T13	2648	0	0	0
T14	0	2	0	0
T15	5849	0	0	0
T27	0	2	0	0
T33	8799	1	0	0
T46	0	38	0	0
T49	0	1	0	0
T79	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51332150	12111	0	0
T1	11492	2	0	0
T2	12376	3	0	0
T3	209020	63	0	0
T4	15503	4	0	0
T5	14531	3	0	0
T6	20864	14	0	0
T7	23449	0	0	0
T8	12069	4	0	0
T9	12758	5	0	0
T10	210184	66	0	0
T11	0	8	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51332150	1028	0	0
T1	11492	2	0	0
T2	12376	0	0	0
T3	209020	0	0	0
T4	15503	0	0	0
T5	14531	0	0	0
T6	20864	0	0	0
T7	23449	0	0	0
T8	12069	4	0	0
T9	12758	5	0	0
T10	210184	0	0	0
T14	0	1	0	0
T27	0	4	0	0
T33	0	2	0	0
T46	0	45	0	0
T72	0	4	0	0
T73	0	4	0	0
T79	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51332150	12111	0	0
T1	11492	2	0	0
T2	12376	3	0	0
T3	209020	63	0	0
T4	15503	4	0	0
T5	14531	3	0	0
T6	20864	14	0	0
T7	23449	0	0	0
T8	12069	4	0	0
T9	12758	5	0	0
T10	210184	66	0	0
T11	0	8	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51332150	1028	0	0
T1	11492	2	0	0
T2	12376	0	0	0
T3	209020	0	0	0
T4	15503	0	0	0
T5	14531	0	0	0
T6	20864	0	0	0
T7	23449	0	0	0
T8	12069	4	0	0
T9	12758	5	0	0
T10	210184	0	0	0
T14	0	1	0	0
T27	0	4	0	0
T33	0	2	0	0
T46	0	45	0	0
T72	0	4	0	0
T73	0	4	0	0
T79	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666601	12138	0	0
T1	5746	3	0	0
T2	6185	4	0	0
T3	104552	63	0	0
T4	7752	4	0	0
T5	7262	3	0	0
T6	10432	14	0	0
T7	11728	0	0	0
T8	6034	5	0	0
T9	6379	4	0	0
T10	105082	66	0	0
T11	0	8	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666601	1013	0	0
T1	5746	3	0	0
T2	6185	1	0	0
T3	104552	0	0	0
T4	7752	0	0	0
T5	7262	0	0	0
T6	10432	0	0	0
T7	11728	0	0	0
T8	6034	5	0	0
T9	6379	4	0	0
T10	105082	0	0	0
T27	0	4	0	0
T33	0	3	0	0
T45	0	1	0	0
T46	0	36	0	0
T72	0	5	0	0
T73	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666601	12138	0	0
T1	5746	3	0	0
T2	6185	4	0	0
T3	104552	63	0	0
T4	7752	4	0	0
T5	7262	3	0	0
T6	10432	14	0	0
T7	11728	0	0	0
T8	6034	5	0	0
T9	6379	4	0	0
T10	105082	66	0	0
T11	0	8	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666601	1013	0	0
T1	5746	3	0	0
T2	6185	1	0	0
T3	104552	0	0	0
T4	7752	0	0	0
T5	7262	0	0	0
T6	10432	0	0	0
T7	11728	0	0	0
T8	6034	5	0	0
T9	6379	4	0	0
T10	105082	0	0	0
T27	0	4	0	0
T33	0	3	0	0
T45	0	1	0	0
T46	0	36	0	0
T72	0	5	0	0
T73	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666877	12201	0	0
T1	5746	3	0	0
T2	6184	3	0	0
T3	104547	63	0	0
T4	7752	4	0	0
T5	7263	3	0	0
T6	10432	14	0	0
T7	11732	0	0	0
T8	6034	5	0	0
T9	6378	5	0	0
T10	105103	66	0	0
T11	0	8	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666877	1073	0	0
T1	5746	3	0	0
T2	6184	0	0	0
T3	104547	0	0	0
T4	7752	0	0	0
T5	7263	0	0	0
T6	10432	0	0	0
T7	11732	0	0	0
T8	6034	5	0	0
T9	6378	5	0	0
T10	105103	0	0	0
T27	0	5	0	0
T33	0	4	0	0
T45	0	1	0	0
T46	0	38	0	0
T72	0	5	0	0
T73	0	7	0	0
T74	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666877	12201	0	0
T1	5746	3	0	0
T2	6184	3	0	0
T3	104547	63	0	0
T4	7752	4	0	0
T5	7263	3	0	0
T6	10432	14	0	0
T7	11732	0	0	0
T8	6034	5	0	0
T9	6378	5	0	0
T10	105103	66	0	0
T11	0	8	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25666877	1073	0	0
T1	5746	3	0	0
T2	6184	0	0	0
T3	104547	0	0	0
T4	7752	0	0	0
T5	7263	0	0	0
T6	10432	0	0	0
T7	11732	0	0	0
T8	6034	5	0	0
T9	6378	5	0	0
T10	105103	0	0	0
T27	0	5	0	0
T33	0	4	0	0
T45	0	1	0	0
T46	0	38	0	0
T72	0	5	0	0
T73	0	7	0	0
T74	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1619488	20985	0	0
T1	357	5	0	0
T2	385	6	0	0
T3	6549	96	0	0
T4	484	6	0	0
T5	452	6	0	0
T6	651	15	0	0
T7	735	3	0	0
T8	375	8	0	0
T9	397	9	0	0
T10	6583	91	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1619488	1111	0	0
T1	357	4	0	0
T2	385	0	0	0
T3	6549	0	0	0
T4	484	0	0	0
T5	452	0	0	0
T6	651	0	0	0
T7	735	0	0	0
T8	375	7	0	0
T9	397	8	0	0
T10	6583	0	0	0
T27	0	6	0	0
T33	0	5	0	0
T46	0	40	0	0
T72	0	7	0	0
T73	0	8	0	0
T80	0	13	0	0
T81	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1619488	20985	0	0
T1	357	5	0	0
T2	385	6	0	0
T3	6549	96	0	0
T4	484	6	0	0
T5	452	6	0	0
T6	651	15	0	0
T7	735	3	0	0
T8	375	8	0	0
T9	397	9	0	0
T10	6583	91	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1619488	1111	0	0
T1	357	4	0	0
T2	385	0	0	0
T3	6549	0	0	0
T4	484	0	0	0
T5	452	0	0	0
T6	651	0	0	0
T7	735	0	0	0
T8	375	7	0	0
T9	397	8	0	0
T10	6583	0	0	0
T27	0	6	0	0
T33	0	5	0	0
T46	0	40	0	0
T72	0	7	0	0
T73	0	8	0	0
T80	0	13	0	0
T81	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	13614	0	0
T1	2872	6	0	0
T2	3092	5	0	0
T3	52279	75	0	0
T4	3876	4	0	0
T5	3631	4	0	0
T6	5216	14	0	0
T7	5866	0	0	0
T8	3016	8	0	0
T9	3189	8	0	0
T10	52546	75	0	0
T11	0	9	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	1160	0	0
T1	2872	6	0	0
T2	3092	1	0	0
T3	52279	0	0	0
T4	3876	0	0	0
T5	3631	0	0	0
T6	5216	0	0	0
T7	5866	0	0	0
T8	3016	8	0	0
T9	3189	8	0	0
T10	52546	0	0	0
T27	0	8	0	0
T28	0	1	0	0
T33	0	5	0	0
T46	0	40	0	0
T72	0	8	0	0
T73	0	9	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	13614	0	0
T1	2872	6	0	0
T2	3092	5	0	0
T3	52279	75	0	0
T4	3876	4	0	0
T5	3631	4	0	0
T6	5216	14	0	0
T7	5866	0	0	0
T8	3016	8	0	0
T9	3189	8	0	0
T10	52546	75	0	0
T11	0	9	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	1160	0	0
T1	2872	6	0	0
T2	3092	1	0	0
T3	52279	0	0	0
T4	3876	0	0	0
T5	3631	0	0	0
T6	5216	0	0	0
T7	5866	0	0	0
T8	3016	8	0	0
T9	3189	8	0	0
T10	52546	0	0	0
T27	0	8	0	0
T28	0	1	0	0
T33	0	5	0	0
T46	0	40	0	0
T72	0	8	0	0
T73	0	9	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	13688	0	0
T1	2872	7	0	0
T2	3092	4	0	0
T3	52279	75	0	0
T4	3876	4	0	0
T5	3631	4	0	0
T6	5216	14	0	0
T7	5866	0	0	0
T8	3016	8	0	0
T9	3189	8	0	0
T10	52546	75	0	0
T11	0	9	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	1241	0	0
T1	2872	7	0	0
T2	3092	0	0	0
T3	52279	0	0	0
T4	3876	0	0	0
T5	3631	0	0	0
T6	5216	0	0	0
T7	5866	0	0	0
T8	3016	8	0	0
T9	3189	8	0	0
T10	52546	0	0	0
T27	0	8	0	0
T33	0	6	0	0
T46	0	40	0	0
T72	0	8	0	0
T73	0	9	0	0
T80	0	12	0	0
T81	0	9	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	13688	0	0
T1	2872	7	0	0
T2	3092	4	0	0
T3	52279	75	0	0
T4	3876	4	0	0
T5	3631	4	0	0
T6	5216	14	0	0
T7	5866	0	0	0
T8	3016	8	0	0
T9	3189	8	0	0
T10	52546	75	0	0
T11	0	9	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	1241	0	0
T1	2872	7	0	0
T2	3092	0	0	0
T3	52279	0	0	0
T4	3876	0	0	0
T5	3631	0	0	0
T6	5216	0	0	0
T7	5866	0	0	0
T8	3016	8	0	0
T9	3189	8	0	0
T10	52546	0	0	0
T27	0	8	0	0
T33	0	6	0	0
T46	0	40	0	0
T72	0	8	0	0
T73	0	9	0	0
T80	0	12	0	0
T81	0	9	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	13732	0	0
T1	2872	8	0	0
T2	3092	4	0	0
T3	52279	75	0	0
T4	3876	4	0	0
T5	3631	4	0	0
T6	5216	14	0	0
T7	5866	0	0	0
T8	3016	10	0	0
T9	3189	9	0	0
T10	52546	75	0	0
T11	0	9	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	1283	0	0
T1	2872	8	0	0
T2	3092	0	0	0
T3	52279	0	0	0
T4	3876	0	0	0
T5	3631	0	0	0
T6	5216	0	0	0
T7	5866	0	0	0
T8	3016	10	0	0
T9	3189	9	0	0
T10	52546	0	0	0
T27	0	10	0	0
T33	0	8	0	0
T45	0	1	0	0
T46	0	40	0	0
T72	0	10	0	0
T73	0	11	0	0
T74	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	13732	0	0
T1	2872	8	0	0
T2	3092	4	0	0
T3	52279	75	0	0
T4	3876	4	0	0
T5	3631	4	0	0
T6	5216	14	0	0
T7	5866	0	0	0
T8	3016	10	0	0
T9	3189	9	0	0
T10	52546	75	0	0
T11	0	9	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12832986	1283	0	0
T1	2872	8	0	0
T2	3092	0	0	0
T3	52279	0	0	0
T4	3876	0	0	0
T5	3631	0	0	0
T6	5216	0	0	0
T7	5866	0	0	0
T8	3016	10	0	0
T9	3189	9	0	0
T10	52546	0	0	0
T27	0	10	0	0
T33	0	8	0	0
T45	0	1	0	0
T46	0	40	0	0
T72	0	10	0	0
T73	0	11	0	0
T74	0	1	0	0