Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12212498	8285	0	0
alert_regwen_rd_A	12212498	4130	0	0
cpu_regwen_rd_A	12212498	4264	0	0
sw_rst_ctrl_n_0_rd_A	12212498	7412	0	0
sw_rst_ctrl_n_1_rd_A	12212498	7579	0	0
sw_rst_ctrl_n_2_rd_A	12212498	7343	0	0
sw_rst_ctrl_n_3_rd_A	12212498	7580	0	0
sw_rst_ctrl_n_4_rd_A	12212498	7550	0	0
sw_rst_ctrl_n_5_rd_A	12212498	7605	0	0
sw_rst_ctrl_n_6_rd_A	12212498	7595	0	0
sw_rst_ctrl_n_7_rd_A	12212498	7766	0	0
sw_rst_regwen_0_rd_A	12212498	4563	0	0
sw_rst_regwen_1_rd_A	12212498	4434	0	0
sw_rst_regwen_2_rd_A	12212498	4741	0	0
sw_rst_regwen_3_rd_A	12212498	4635	0	0
sw_rst_regwen_4_rd_A	12212498	4381	0	0
sw_rst_regwen_5_rd_A	12212498	4446	0	0
sw_rst_regwen_6_rd_A	12212498	4809	0	0
sw_rst_regwen_7_rd_A	12212498	4685	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	8285	0	0
T59	19547	2	0	0
T63	2696	43	0	0
T64	2886	12	0	0
T65	2580	24	0	0
T66	10940	2	0	0
T67	16363	1	0	0
T82	3112	11	0	0
T83	3592	330	0	0
T84	4408	21	0	0
T85	4637	672	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	4130	0	0
T32	36240	8	0	0
T43	5087	0	0	0
T44	1802	0	0	0
T45	4510	0	0	0
T46	120224	0	0	0
T47	5486	0	0	0
T48	1559	0	0	0
T49	5450	0	0	0
T55	370701	0	0	0
T56	26750	0	0	0
T93	0	60	0	0
T95	0	63	0	0
T98	0	108	0	0
T103	0	227	0	0
T106	0	110	0	0
T129	0	44	0	0
T130	0	98	0	0
T131	0	34	0	0
T132	0	37	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	4264	0	0
T32	36240	27	0	0
T43	5087	0	0	0
T44	1802	0	0	0
T45	4510	0	0	0
T46	120224	0	0	0
T47	5486	0	0	0
T48	1559	0	0	0
T49	5450	0	0	0
T55	370701	0	0	0
T56	26750	0	0	0
T93	0	62	0	0
T95	0	48	0	0
T98	0	125	0	0
T103	0	240	0	0
T106	0	103	0	0
T129	0	53	0	0
T130	0	88	0	0
T131	0	32	0	0
T132	0	40	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	7412	0	0
T6	4189	32	0	0
T7	5320	0	0	0
T8	2974	0	0	0
T9	3122	0	0	0
T10	49192	0	0	0
T11	2715	0	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T15	5689	0	0	0
T27	0	130	0	0
T32	0	30	0	0
T33	8709	127	0	0
T49	0	7	0	0
T73	0	146	0	0
T77	0	58	0	0
T133	0	7	0	0
T134	0	25	0	0
T135	0	15	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	7579	0	0
T6	4189	19	0	0
T7	5320	0	0	0
T8	2974	0	0	0
T9	3122	0	0	0
T10	49192	0	0	0
T11	2715	0	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T15	5689	0	0	0
T27	0	167	0	0
T32	0	29	0	0
T33	8709	139	0	0
T49	0	3	0	0
T73	0	147	0	0
T77	0	45	0	0
T133	0	10	0	0
T134	0	43	0	0
T136	0	1	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	7343	0	0
T6	4189	28	0	0
T7	5320	0	0	0
T8	2974	0	0	0
T9	3122	0	0	0
T10	49192	0	0	0
T11	2715	0	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T15	5689	0	0	0
T27	0	147	0	0
T32	0	50	0	0
T33	8709	117	0	0
T49	0	9	0	0
T73	0	129	0	0
T77	0	68	0	0
T133	0	7	0	0
T134	0	34	0	0
T136	0	6	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	7580	0	0
T6	4189	30	0	0
T7	5320	0	0	0
T8	2974	0	0	0
T9	3122	0	0	0
T10	49192	0	0	0
T11	2715	0	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T15	5689	0	0	0
T27	0	149	0	0
T32	0	36	0	0
T33	8709	133	0	0
T49	0	1	0	0
T73	0	162	0	0
T77	0	62	0	0
T133	0	15	0	0
T134	0	41	0	0
T136	0	5	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	7550	0	0
T6	4189	32	0	0
T7	5320	0	0	0
T8	2974	0	0	0
T9	3122	0	0	0
T10	49192	0	0	0
T11	2715	0	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T15	5689	0	0	0
T27	0	127	0	0
T32	0	35	0	0
T33	8709	119	0	0
T49	0	6	0	0
T73	0	148	0	0
T77	0	74	0	0
T133	0	11	0	0
T134	0	46	0	0
T136	0	3	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	7605	0	0
T6	4189	35	0	0
T7	5320	0	0	0
T8	2974	0	0	0
T9	3122	0	0	0
T10	49192	0	0	0
T11	2715	0	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T15	5689	0	0	0
T27	0	150	0	0
T32	0	27	0	0
T33	8709	128	0	0
T49	0	3	0	0
T73	0	171	0	0
T77	0	56	0	0
T133	0	17	0	0
T134	0	32	0	0
T136	0	7	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	7595	0	0
T6	4189	46	0	0
T7	5320	0	0	0
T8	2974	0	0	0
T9	3122	0	0	0
T10	49192	0	0	0
T11	2715	0	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T15	5689	0	0	0
T27	0	147	0	0
T32	0	33	0	0
T33	8709	139	0	0
T49	0	12	0	0
T73	0	158	0	0
T77	0	60	0	0
T133	0	11	0	0
T134	0	32	0	0
T136	0	2	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	7766	0	0
T6	4189	34	0	0
T7	5320	0	0	0
T8	2974	0	0	0
T9	3122	0	0	0
T10	49192	0	0	0
T11	2715	0	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T15	5689	0	0	0
T27	0	138	0	0
T32	0	31	0	0
T33	8709	114	0	0
T49	0	23	0	0
T73	0	172	0	0
T77	0	46	0	0
T133	0	14	0	0
T134	0	38	0	0
T136	0	1	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	4563	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T14	1611	0	0	0
T15	5689	0	0	0
T16	4134	0	0	0
T17	3588	0	0	0
T26	1704	0	0	0
T27	0	25	0	0
T32	0	26	0	0
T33	8709	25	0	0
T49	0	7	0	0
T73	0	24	0	0
T78	5915	0	0	0
T79	2314	0	0	0
T93	0	64	0	0
T95	0	15	0	0
T98	0	127	0	0
T137	0	3	0	0
T138	0	49	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	4434	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T14	1611	0	0	0
T15	5689	0	0	0
T16	4134	0	0	0
T17	3588	0	0	0
T26	1704	0	0	0
T27	0	31	0	0
T32	0	38	0	0
T33	8709	30	0	0
T49	0	2	0	0
T73	0	39	0	0
T78	5915	0	0	0
T79	2314	0	0	0
T93	0	76	0	0
T95	0	28	0	0
T98	0	130	0	0
T137	0	8	0	0
T138	0	21	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	4741	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T14	1611	0	0	0
T15	5689	0	0	0
T16	4134	0	0	0
T17	3588	0	0	0
T26	1704	0	0	0
T27	0	31	0	0
T32	0	23	0	0
T33	8709	43	0	0
T49	0	1	0	0
T73	0	24	0	0
T78	5915	0	0	0
T79	2314	0	0	0
T93	0	72	0	0
T95	0	25	0	0
T98	0	106	0	0
T137	0	11	0	0
T138	0	30	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	4635	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T14	1611	0	0	0
T15	5689	0	0	0
T16	4134	0	0	0
T17	3588	0	0	0
T26	1704	0	0	0
T27	0	34	0	0
T32	0	43	0	0
T33	8709	40	0	0
T49	0	6	0	0
T73	0	34	0	0
T78	5915	0	0	0
T79	2314	0	0	0
T93	0	62	0	0
T95	0	27	0	0
T98	0	129	0	0
T137	0	5	0	0
T138	0	40	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	4381	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T14	1611	0	0	0
T15	5689	0	0	0
T16	4134	0	0	0
T17	3588	0	0	0
T26	1704	0	0	0
T27	0	35	0	0
T32	0	34	0	0
T33	8709	27	0	0
T73	0	37	0	0
T78	5915	0	0	0
T79	2314	0	0	0
T93	0	43	0	0
T95	0	25	0	0
T98	0	134	0	0
T137	0	8	0	0
T138	0	31	0	0
T139	0	4	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	4446	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T14	1611	0	0	0
T15	5689	0	0	0
T16	4134	0	0	0
T17	3588	0	0	0
T26	1704	0	0	0
T27	0	32	0	0
T32	0	18	0	0
T33	8709	33	0	0
T49	0	5	0	0
T73	0	22	0	0
T78	5915	0	0	0
T79	2314	0	0	0
T93	0	73	0	0
T95	0	22	0	0
T98	0	129	0	0
T137	0	1	0	0
T138	0	41	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	4809	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T14	1611	0	0	0
T15	5689	0	0	0
T16	4134	0	0	0
T17	3588	0	0	0
T26	1704	0	0	0
T27	0	43	0	0
T32	0	40	0	0
T33	8709	36	0	0
T49	0	11	0	0
T73	0	24	0	0
T78	5915	0	0	0
T79	2314	0	0	0
T93	0	65	0	0
T95	0	36	0	0
T98	0	183	0	0
T137	0	8	0	0
T138	0	39	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12212498	4685	0	0
T12	3171	0	0	0
T13	2356	0	0	0
T14	1611	0	0	0
T15	5689	0	0	0
T16	4134	0	0	0
T17	3588	0	0	0
T26	1704	0	0	0
T27	0	20	0	0
T32	0	42	0	0
T33	8709	19	0	0
T73	0	28	0	0
T78	5915	0	0	0
T79	2314	0	0	0
T93	0	49	0	0
T95	0	34	0	0
T98	0	155	0	0
T106	0	99	0	0
T138	0	26	0	0
T139	0	14	0	0