Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	636170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

381953

1

T1

841

T2

52

T3

63

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	544396	1			T1	1298		T2	63		T3	99
values[0x0]	236516	1			T1	522		T2	35		T3	65
values[0x1]	237211	1			T1	528		T2	31		T3	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	533941	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

484182

1

T1

1060

T2

67

T3

80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3313	1			T5	81		T10	1		T11	9
valid_sources[0x01]	3133	1			T5	85		T10	1		T11	6
valid_sources[0x02]	3801	1			T3	2		T5	65		T11	2
valid_sources[0x03]	3901	1			T3	2		T5	70		T6	408
valid_sources[0x04]	4202	1			T3	1		T5	61		T6	480
valid_sources[0x05]	3358	1			T3	3		T5	87		T6	155
valid_sources[0x06]	3339	1			T5	86		T11	2		T13	5
valid_sources[0x07]	4059	1			T3	1		T5	74		T10	1
valid_sources[0x08]	3896	1			T5	83		T12	127		T13	13
valid_sources[0x09]	3772	1			T5	69		T13	13		T26	13
valid_sources[0x0a]	3081	1			T3	4		T5	73		T10	2
valid_sources[0x0b]	3601	1			T5	64		T13	6		T26	6
valid_sources[0x0c]	5735	1			T5	97		T13	7		T26	14
valid_sources[0x0d]	3987	1			T3	1		T5	80		T10	1
valid_sources[0x0e]	3339	1			T3	1		T5	72		T10	1
valid_sources[0x0f]	3467	1			T5	90		T6	238		T10	1
valid_sources[0x10]	3687	1			T5	82		T10	1		T11	2
valid_sources[0x11]	10501	1			T3	1		T4	10		T5	82
valid_sources[0x12]	3504	1			T5	93		T10	3		T11	2
valid_sources[0x13]	3404	1			T5	76		T10	1		T11	1
valid_sources[0x14]	2950	1			T3	1		T5	71		T10	1
valid_sources[0x15]	3944	1			T5	72		T6	154		T13	22
valid_sources[0x16]	4038	1			T5	61		T11	5		T13	16
valid_sources[0x17]	3446	1			T3	1		T5	72		T13	10
valid_sources[0x18]	3819	1			T3	1		T5	93		T10	3
valid_sources[0x19]	5062	1			T3	5		T5	67		T6	70
valid_sources[0x1a]	4741	1			T1	223		T3	1		T5	79
valid_sources[0x1b]	4404	1			T5	56		T13	7		T26	12
valid_sources[0x1c]	4147	1			T3	2		T5	90		T10	1
valid_sources[0x1d]	4597	1			T5	98		T10	1		T13	14
valid_sources[0x1e]	3609	1			T3	2		T5	74		T10	1
valid_sources[0x1f]	3863	1			T3	3		T5	90		T10	1
valid_sources[0x20]	3217	1			T5	90		T13	14		T26	8
valid_sources[0x21]	3555	1			T5	90		T10	4		T11	4
valid_sources[0x22]	3375	1			T3	1		T5	63		T10	1
valid_sources[0x23]	3702	1			T3	1		T5	83		T11	1
valid_sources[0x24]	6735	1			T3	3		T5	67		T6	154
valid_sources[0x25]	3706	1			T3	2		T5	59		T6	113
valid_sources[0x26]	3528	1			T3	1		T5	93		T10	2
valid_sources[0x27]	4319	1			T5	82		T13	12		T26	15
valid_sources[0x28]	3397	1			T3	1		T5	79		T6	70
valid_sources[0x29]	3972	1			T3	1		T5	78		T10	1
valid_sources[0x2a]	3530	1			T3	2		T5	83		T10	1
valid_sources[0x2b]	3449	1			T5	84		T11	3		T13	17
valid_sources[0x2c]	7118	1			T3	1		T5	75		T13	12
valid_sources[0x2d]	4064	1			T5	71		T10	1		T13	15
valid_sources[0x2e]	3743	1			T3	2		T5	76		T6	70
valid_sources[0x2f]	3346	1			T1	2		T5	85		T6	70
valid_sources[0x30]	3753	1			T1	230		T3	1		T5	79
valid_sources[0x31]	3253	1			T3	1		T5	106		T10	1
valid_sources[0x32]	6911	1			T5	80		T11	1		T13	14
valid_sources[0x33]	5678	1			T3	3		T5	88		T6	1283
valid_sources[0x34]	4279	1			T3	1		T5	72		T10	1
valid_sources[0x35]	5992	1			T5	80		T6	70		T10	1
valid_sources[0x36]	4443	1			T5	63		T10	1		T12	78
valid_sources[0x37]	4283	1			T3	2		T5	93		T10	1
valid_sources[0x38]	3551	1			T3	1		T5	99		T13	10
valid_sources[0x39]	3543	1			T5	71		T10	2		T12	31
valid_sources[0x3a]	4239	1			T3	1		T5	70		T10	2
valid_sources[0x3b]	3602	1			T5	84		T13	15		T26	7
valid_sources[0x3c]	3187	1			T5	71		T10	1		T13	12
valid_sources[0x3d]	3888	1			T3	1		T5	86		T12	5
valid_sources[0x3e]	3353	1			T5	92		T10	2		T11	1
valid_sources[0x3f]	3089	1			T5	87		T13	23		T26	7
valid_sources[0x40]	5407	1			T3	1		T5	79		T13	12
valid_sources[0x41]	3562	1			T3	1		T5	72		T10	3
valid_sources[0x42]	3644	1			T5	78		T6	113		T13	12
valid_sources[0x43]	3519	1			T3	1		T5	80		T6	70
valid_sources[0x44]	3361	1			T5	75		T13	8		T26	5
valid_sources[0x45]	2974	1			T3	1		T5	72		T10	1
valid_sources[0x46]	3826	1			T5	85		T6	70		T10	1
valid_sources[0x47]	3118	1			T3	1		T5	86		T10	2
valid_sources[0x48]	4674	1			T3	1		T5	80		T6	814
valid_sources[0x49]	3050	1			T3	2		T5	80		T10	1
valid_sources[0x4a]	3610	1			T5	95		T10	1		T13	15
valid_sources[0x4b]	3177	1			T5	96		T11	1		T13	4
valid_sources[0x4c]	3965	1			T1	241		T5	90		T13	13
valid_sources[0x4d]	3338	1			T5	66		T10	1		T11	3
valid_sources[0x4e]	3599	1			T3	1		T5	84		T10	3
valid_sources[0x4f]	4094	1			T3	2		T5	70		T6	112
valid_sources[0x50]	3167	1			T5	91		T13	15		T26	8
valid_sources[0x51]	3509	1			T3	2		T5	85		T10	1
valid_sources[0x52]	3526	1			T3	2		T5	68		T10	1
valid_sources[0x53]	4234	1			T3	2		T5	84		T6	327
valid_sources[0x54]	3245	1			T5	71		T11	1		T13	11
valid_sources[0x55]	3192	1			T2	129		T5	65		T10	1
valid_sources[0x56]	3678	1			T5	88		T10	2		T11	2
valid_sources[0x57]	3348	1			T3	1		T5	70		T10	1
valid_sources[0x58]	3531	1			T3	1		T5	73		T10	3
valid_sources[0x59]	3866	1			T5	67		T10	1		T13	8
valid_sources[0x5a]	3658	1			T3	1		T5	83		T6	70
valid_sources[0x5b]	4457	1			T5	85		T6	113		T10	1
valid_sources[0x5c]	5310	1			T5	75		T6	409		T13	9
valid_sources[0x5d]	4183	1			T5	99		T13	13		T26	13
valid_sources[0x5e]	3573	1			T3	2		T5	82		T10	1
valid_sources[0x5f]	4515	1			T5	78		T11	2		T13	10
valid_sources[0x60]	3495	1			T3	1		T5	86		T11	1
valid_sources[0x61]	3689	1			T5	102		T6	364		T10	2
valid_sources[0x62]	3691	1			T3	2		T5	105		T10	1
valid_sources[0x63]	3940	1			T1	238		T3	1		T5	70
valid_sources[0x64]	3030	1			T3	2		T5	89		T11	1
valid_sources[0x65]	3828	1			T5	95		T11	1		T13	14
valid_sources[0x66]	3116	1			T3	1		T5	76		T10	4
valid_sources[0x67]	4419	1			T5	91		T6	113		T10	1
valid_sources[0x68]	3733	1			T5	75		T11	1		T13	29
valid_sources[0x69]	3542	1			T3	1		T5	82		T13	5
valid_sources[0x6a]	7057	1			T5	79		T13	11		T26	10
valid_sources[0x6b]	3217	1			T5	79		T10	2		T13	4
valid_sources[0x6c]	3396	1			T5	73		T10	1		T12	10
valid_sources[0x6d]	3633	1			T5	98		T10	2		T11	1
valid_sources[0x6e]	4064	1			T5	68		T11	2		T13	13
valid_sources[0x6f]	3006	1			T3	1		T5	84		T10	1
valid_sources[0x70]	3574	1			T5	88		T10	3		T13	11
valid_sources[0x71]	7688	1			T5	82		T10	1		T11	3
valid_sources[0x72]	3249	1			T3	1		T5	87		T10	2
valid_sources[0x73]	3455	1			T5	69		T6	113		T13	15
valid_sources[0x74]	3814	1			T3	1		T5	75		T11	2
valid_sources[0x75]	4972	1			T5	90		T11	5		T13	8
valid_sources[0x76]	3534	1			T3	1		T5	66		T10	2
valid_sources[0x77]	6213	1			T5	97		T10	1		T13	7
valid_sources[0x78]	3392	1			T1	101		T5	78		T13	13
valid_sources[0x79]	4261	1			T3	1		T5	89		T6	112
valid_sources[0x7a]	3843	1			T3	1		T5	87		T10	1
valid_sources[0x7b]	3455	1			T5	89		T23	1		T13	14
valid_sources[0x7c]	3389	1			T3	1		T5	70		T10	3
valid_sources[0x7d]	4141	1			T3	1		T5	67		T13	9
valid_sources[0x7e]	3673	1			T1	6		T5	79		T6	464
valid_sources[0x7f]	6636	1			T3	1		T5	85		T10	2
valid_sources[0x80]	3483	1			T1	2		T5	72		T13	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

255291

1

T1

582

T2

31

T3

38

values[0x0]

all_enables

biggest_size

82567

1

T1

171

T2

15

T3

19

values[0x1]

all_enables

biggest_size

44095

1

T1

88

T2

6

T3

6