Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56977563	8566	0	0
CascadeEffAonToRstPorAboveRise_A	56977563	8566	0	0
CascadeEffAonToRstPorIoAboveFall_A	54696787	8566	0	0
CascadeEffAonToRstPorIoAboveRise_A	54696787	8566	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27349105	8566	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27349105	8566	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13674448	8566	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13674448	8566	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27349410	8566	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27349410	8566	0	0
CascadeLcToLcAboveFall_A	56977563	22128	0	0
CascadeLcToLcAboveRise_A	56977563	22128	0	0
CascadeLcToLcAonAboveFall_A	1726282	22128	0	0
CascadeLcToLcAonAboveRise_A	1726282	22128	0	0
CascadeLcToLcShadowedAboveFall_A	56977563	22128	0	0
CascadeLcToLcShadowedAboveRise_A	56977563	22128	0	0
CascadePorToAonAboveFall_A	1726282	6666	0	0
CascadeSysToSysAboveFall_A	56977563	22128	0	0
CascadeSysToSysAboveRise_A	56977563	22128	0	0
ScanRstToAonRise_A	1726282	212	0	0
StablePorToAonRise_A	1726282	8566	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12139662	22128	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12139662	22128	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12139662	22128	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12139662	22128	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13674448	22128	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13674448	22128	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12139662	22128	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12139662	22128	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12139662	22128	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12139662	22128	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56977563	8566	0	0
T1	155333	15	0	0
T2	14555	1	0	0
T3	14894	2	0	0
T4	7985	1	0	0
T5	116554	117	0	0
T6	753815	86	0	0
T7	121410	27	0	0
T8	22918	2	0	0
T9	24280	8	0	0
T10	10041	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56977563	8566	0	0
T1	155333	15	0	0
T2	14555	1	0	0
T3	14894	2	0	0
T4	7985	1	0	0
T5	116554	117	0	0
T6	753815	86	0	0
T7	121410	27	0	0
T8	22918	2	0	0
T9	24280	8	0	0
T10	10041	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54696787	8566	0	0
T1	149117	15	0	0
T2	13972	1	0	0
T3	14294	2	0	0
T4	7665	1	0	0
T5	111890	117	0	0
T6	723637	86	0	0
T7	116535	27	0	0
T8	22001	2	0	0
T9	23330	8	0	0
T10	9647	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54696787	8566	0	0
T1	149117	15	0	0
T2	13972	1	0	0
T3	14294	2	0	0
T4	7665	1	0	0
T5	111890	117	0	0
T6	723637	86	0	0
T7	116535	27	0	0
T8	22001	2	0	0
T9	23330	8	0	0
T10	9647	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349105	8566	0	0
T1	74568	15	0	0
T2	6985	1	0	0
T3	7149	2	0	0
T4	3831	1	0	0
T5	559468	117	0	0
T6	361814	86	0	0
T7	58256	27	0	0
T8	11001	2	0	0
T9	11661	8	0	0
T10	4820	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349105	8566	0	0
T1	74568	15	0	0
T2	6985	1	0	0
T3	7149	2	0	0
T4	3831	1	0	0
T5	559468	117	0	0
T6	361814	86	0	0
T7	58256	27	0	0
T8	11001	2	0	0
T9	11661	8	0	0
T10	4820	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	8566	0	0
T1	37278	15	0	0
T2	3492	1	0	0
T3	3574	2	0	0
T4	1916	1	0	0
T5	279740	117	0	0
T6	180917	86	0	0
T7	29135	27	0	0
T8	5499	2	0	0
T9	5827	8	0	0
T10	2410	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	8566	0	0
T1	37278	15	0	0
T2	3492	1	0	0
T3	3574	2	0	0
T4	1916	1	0	0
T5	279740	117	0	0
T6	180917	86	0	0
T7	29135	27	0	0
T8	5499	2	0	0
T9	5827	8	0	0
T10	2410	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349410	8566	0	0
T1	74566	15	0	0
T2	6986	1	0	0
T3	7149	2	0	0
T4	3831	1	0	0
T5	559463	117	0	0
T6	361841	86	0	0
T7	58265	27	0	0
T8	11000	2	0	0
T9	11653	8	0	0
T10	4819	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349410	8566	0	0
T1	74566	15	0	0
T2	6986	1	0	0
T3	7149	2	0	0
T4	3831	1	0	0
T5	559463	117	0	0
T6	361841	86	0	0
T7	58265	27	0	0
T8	11000	2	0	0
T9	11653	8	0	0
T10	4819	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56977563	22128	0	0
T1	155333	47	0	0
T2	14555	8	0	0
T3	14894	6	0	0
T4	7985	1	0	0
T5	116554	393	0	0
T6	753815	282	0	0
T7	121410	102	0	0
T8	22918	2	0	0
T9	24280	8	0	0
T10	10041	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56977563	22128	0	0
T1	155333	47	0	0
T2	14555	8	0	0
T3	14894	6	0	0
T4	7985	1	0	0
T5	116554	393	0	0
T6	753815	282	0	0
T7	121410	102	0	0
T8	22918	2	0	0
T9	24280	8	0	0
T10	10041	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726282	22128	0	0
T1	4727	47	0	0
T2	436	8	0	0
T3	446	6	0	0
T4	239	1	0	0
T5	35439	393	0	0
T6	22994	282	0	0
T7	3656	102	0	0
T8	687	2	0	0
T9	730	8	0	0
T10	299	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726282	22128	0	0
T1	4727	47	0	0
T2	436	8	0	0
T3	446	6	0	0
T4	239	1	0	0
T5	35439	393	0	0
T6	22994	282	0	0
T7	3656	102	0	0
T8	687	2	0	0
T9	730	8	0	0
T10	299	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56977563	22128	0	0
T1	155333	47	0	0
T2	14555	8	0	0
T3	14894	6	0	0
T4	7985	1	0	0
T5	116554	393	0	0
T6	753815	282	0	0
T7	121410	102	0	0
T8	22918	2	0	0
T9	24280	8	0	0
T10	10041	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56977563	22128	0	0
T1	155333	47	0	0
T2	14555	8	0	0
T3	14894	6	0	0
T4	7985	1	0	0
T5	116554	393	0	0
T6	753815	282	0	0
T7	121410	102	0	0
T8	22918	2	0	0
T9	24280	8	0	0
T10	10041	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726282	6666	0	0
T1	4727	10	0	0
T2	436	1	0	0
T3	446	1	0	0
T4	239	1	0	0
T5	35439	45	0	0
T6	22994	42	0	0
T7	3656	27	0	0
T8	687	19	0	0
T9	730	8	0	0
T10	299	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56977563	22128	0	0
T1	155333	47	0	0
T2	14555	8	0	0
T3	14894	6	0	0
T4	7985	1	0	0
T5	116554	393	0	0
T6	753815	282	0	0
T7	121410	102	0	0
T8	22918	2	0	0
T9	24280	8	0	0
T10	10041	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56977563	22128	0	0
T1	155333	47	0	0
T2	14555	8	0	0
T3	14894	6	0	0
T4	7985	1	0	0
T5	116554	393	0	0
T6	753815	282	0	0
T7	121410	102	0	0
T8	22918	2	0	0
T9	24280	8	0	0
T10	10041	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726282	212	0	0
T1	4727	1	0	0
T2	436	0	0	0
T3	446	0	0	0
T4	239	0	0	0
T5	35439	6	0	0
T6	22994	3	0	0
T7	3656	0	0	0
T8	687	0	0	0
T9	730	0	0	0
T10	299	0	0	0
T45	0	3	0	0
T76	0	2	0	0
T78	0	7	0	0
T91	0	3	0	0
T92	0	1	0	0
T120	0	2	0	0
T121	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726282	8566	0	0
T1	4727	15	0	0
T2	436	1	0	0
T3	446	2	0	0
T4	239	1	0	0
T5	35439	117	0	0
T6	22994	86	0	0
T7	3656	27	0	0
T8	687	2	0	0
T9	730	8	0	0
T10	299	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12139662	22128	0	0
T1	33290	47	0	0
T2	2958	8	0	0
T3	3332	6	0	0
T4	1897	1	0	0
T5	246979	393	0	0
T6	157677	282	0	0
T7	25957	102	0	0
T8	5385	2	0	0
T9	5092	8	0	0
T10	2118	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12139662	22128	0	0
T1	33290	47	0	0
T2	2958	8	0	0
T3	3332	6	0	0
T4	1897	1	0	0
T5	246979	393	0	0
T6	157677	282	0	0
T7	25957	102	0	0
T8	5385	2	0	0
T9	5092	8	0	0
T10	2118	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12139662	22128	0	0
T1	33290	47	0	0
T2	2958	8	0	0
T3	3332	6	0	0
T4	1897	1	0	0
T5	246979	393	0	0
T6	157677	282	0	0
T7	25957	102	0	0
T8	5385	2	0	0
T9	5092	8	0	0
T10	2118	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12139662	22128	0	0
T1	33290	47	0	0
T2	2958	8	0	0
T3	3332	6	0	0
T4	1897	1	0	0
T5	246979	393	0	0
T6	157677	282	0	0
T7	25957	102	0	0
T8	5385	2	0	0
T9	5092	8	0	0
T10	2118	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	22128	0	0
T1	37278	47	0	0
T2	3492	8	0	0
T3	3574	6	0	0
T4	1916	1	0	0
T5	279740	393	0	0
T6	180917	282	0	0
T7	29135	102	0	0
T8	5499	2	0	0
T9	5827	8	0	0
T10	2410	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	22128	0	0
T1	37278	47	0	0
T2	3492	8	0	0
T3	3574	6	0	0
T4	1916	1	0	0
T5	279740	393	0	0
T6	180917	282	0	0
T7	29135	102	0	0
T8	5499	2	0	0
T9	5827	8	0	0
T10	2410	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12139662	22128	0	0
T1	33290	47	0	0
T2	2958	8	0	0
T3	3332	6	0	0
T4	1897	1	0	0
T5	246979	393	0	0
T6	157677	282	0	0
T7	25957	102	0	0
T8	5385	2	0	0
T9	5092	8	0	0
T10	2118	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12139662	22128	0	0
T1	33290	47	0	0
T2	2958	8	0	0
T3	3332	6	0	0
T4	1897	1	0	0
T5	246979	393	0	0
T6	157677	282	0	0
T7	25957	102	0	0
T8	5385	2	0	0
T9	5092	8	0	0
T10	2118	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12139662	22128	0	0
T1	33290	47	0	0
T2	2958	8	0	0
T3	3332	6	0	0
T4	1897	1	0	0
T5	246979	393	0	0
T6	157677	282	0	0
T7	25957	102	0	0
T8	5385	2	0	0
T9	5092	8	0	0
T10	2118	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12139662	22128	0	0
T1	33290	47	0	0
T2	2958	8	0	0
T3	3332	6	0	0
T4	1897	1	0	0
T5	246979	393	0	0
T6	157677	282	0	0
T7	25957	102	0	0
T8	5385	2	0	0
T9	5092	8	0	0
T10	2118	6	0	0