Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T12
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13674448	14516	0	0
gen_assertions[0].RstEnOn_A	13674448	1158	0	0
gen_assertions[0].RstNOff_A	13674448	14516	0	0
gen_assertions[0].RstNOn_A	13674448	1158	0	0
gen_assertions[1].RstEnOff_A	54696787	13172	0	0
gen_assertions[1].RstEnOn_A	54696787	1092	0	0
gen_assertions[1].RstNOff_A	54696787	13172	0	0
gen_assertions[1].RstNOn_A	54696787	1092	0	0
gen_assertions[2].RstEnOff_A	27349105	13235	0	0
gen_assertions[2].RstEnOn_A	27349105	1096	0	0
gen_assertions[2].RstNOff_A	27349105	13235	0	0
gen_assertions[2].RstNOn_A	27349105	1096	0	0
gen_assertions[3].RstEnOff_A	27349410	13262	0	0
gen_assertions[3].RstEnOn_A	27349410	1107	0	0
gen_assertions[3].RstNOff_A	27349410	13262	0	0
gen_assertions[3].RstNOn_A	27349410	1107	0	0
gen_assertions[4].RstEnOff_A	1726282	22031	0	0
gen_assertions[4].RstEnOn_A	1726282	1190	0	0
gen_assertions[4].RstNOff_A	1726282	22031	0	0
gen_assertions[4].RstNOn_A	1726282	1190	0	0
gen_assertions[5].RstEnOff_A	13674448	14720	0	0
gen_assertions[5].RstEnOn_A	13674448	1194	0	0
gen_assertions[5].RstNOff_A	13674448	14720	0	0
gen_assertions[5].RstNOn_A	13674448	1194	0	0
gen_assertions[6].RstEnOff_A	13674448	14807	0	0
gen_assertions[6].RstEnOn_A	13674448	1288	0	0
gen_assertions[6].RstNOff_A	13674448	14807	0	0
gen_assertions[6].RstNOn_A	13674448	1288	0	0
gen_assertions[7].RstEnOff_A	13674448	14827	0	0
gen_assertions[7].RstEnOn_A	13674448	1300	0	0
gen_assertions[7].RstNOff_A	13674448	14827	0	0
gen_assertions[7].RstNOn_A	13674448	1300	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	14516	0	0
T1	37278	32	0	0
T2	3492	7	0	0
T3	3574	4	0	0
T4	1916	0	0	0
T5	279740	291	0	0
T6	180917	213	0	0
T7	29135	75	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	4	0	0
T11	0	5	0	0
T12	0	7	0	0
T13	0	75	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	1158	0	0
T5	279740	18	0	0
T6	180917	17	0	0
T7	29135	0	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	0	0	0
T11	2568	1	0	0
T12	0	7	0	0
T23	1465	0	0	0
T24	5825	0	0	0
T25	1873	0	0	0
T42	0	1	0	0
T43	0	7	0	0
T44	0	1	0	0
T45	0	23	0	0
T75	0	1	0	0
T76	0	11	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	14516	0	0
T1	37278	32	0	0
T2	3492	7	0	0
T3	3574	4	0	0
T4	1916	0	0	0
T5	279740	291	0	0
T6	180917	213	0	0
T7	29135	75	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	4	0	0
T11	0	5	0	0
T12	0	7	0	0
T13	0	75	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	1158	0	0
T5	279740	18	0	0
T6	180917	17	0	0
T7	29135	0	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	0	0	0
T11	2568	1	0	0
T12	0	7	0	0
T23	1465	0	0	0
T24	5825	0	0	0
T25	1873	0	0	0
T42	0	1	0	0
T43	0	7	0	0
T44	0	1	0	0
T45	0	23	0	0
T75	0	1	0	0
T76	0	11	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54696787	13172	0	0
T1	149117	29	0	0
T2	13972	6	0	0
T3	14294	4	0	0
T4	7665	0	0	0
T5	111890	255	0	0
T6	723637	192	0	0
T7	116535	68	0	0
T8	22001	0	0	0
T9	23330	0	0	0
T10	9647	4	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	67	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54696787	1092	0	0
T5	111890	12	0	0
T6	723637	16	0	0
T7	116535	0	0	0
T8	22001	0	0	0
T9	23330	0	0	0
T10	9647	0	0	0
T11	10279	0	0	0
T12	0	7	0	0
T23	5864	0	0	0
T24	23304	0	0	0
T25	7496	0	0	0
T43	0	8	0	0
T44	0	2	0	0
T45	0	20	0	0
T76	0	12	0	0
T77	0	3	0	0
T78	0	20	0	0
T79	0	9	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54696787	13172	0	0
T1	149117	29	0	0
T2	13972	6	0	0
T3	14294	4	0	0
T4	7665	0	0	0
T5	111890	255	0	0
T6	723637	192	0	0
T7	116535	68	0	0
T8	22001	0	0	0
T9	23330	0	0	0
T10	9647	4	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	67	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54696787	1092	0	0
T5	111890	12	0	0
T6	723637	16	0	0
T7	116535	0	0	0
T8	22001	0	0	0
T9	23330	0	0	0
T10	9647	0	0	0
T11	10279	0	0	0
T12	0	7	0	0
T23	5864	0	0	0
T24	23304	0	0	0
T25	7496	0	0	0
T43	0	8	0	0
T44	0	2	0	0
T45	0	20	0	0
T76	0	12	0	0
T77	0	3	0	0
T78	0	20	0	0
T79	0	9	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349105	13235	0	0
T1	74568	29	0	0
T2	6985	6	0	0
T3	7149	4	0	0
T4	3831	0	0	0
T5	559468	258	0	0
T6	361814	191	0	0
T7	58256	68	0	0
T8	11001	0	0	0
T9	11661	0	0	0
T10	4820	4	0	0
T11	0	4	0	0
T12	0	8	0	0
T13	0	67	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349105	1096	0	0
T5	559468	15	0	0
T6	361814	15	0	0
T7	58256	0	0	0
T8	11001	0	0	0
T9	11661	0	0	0
T10	4820	0	0	0
T11	5139	0	0	0
T12	0	8	0	0
T23	2932	0	0	0
T24	11650	0	0	0
T25	3747	0	0	0
T43	0	10	0	0
T44	0	3	0	0
T45	0	24	0	0
T76	0	13	0	0
T77	0	4	0	0
T78	0	17	0	0
T79	0	8	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349105	13235	0	0
T1	74568	29	0	0
T2	6985	6	0	0
T3	7149	4	0	0
T4	3831	0	0	0
T5	559468	258	0	0
T6	361814	191	0	0
T7	58256	68	0	0
T8	11001	0	0	0
T9	11661	0	0	0
T10	4820	4	0	0
T11	0	4	0	0
T12	0	8	0	0
T13	0	67	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349105	1096	0	0
T5	559468	15	0	0
T6	361814	15	0	0
T7	58256	0	0	0
T8	11001	0	0	0
T9	11661	0	0	0
T10	4820	0	0	0
T11	5139	0	0	0
T12	0	8	0	0
T23	2932	0	0	0
T24	11650	0	0	0
T25	3747	0	0	0
T43	0	10	0	0
T44	0	3	0	0
T45	0	24	0	0
T76	0	13	0	0
T77	0	4	0	0
T78	0	17	0	0
T79	0	8	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349410	13262	0	0
T1	74566	29	0	0
T2	6986	6	0	0
T3	7149	4	0	0
T4	3831	0	0	0
T5	559463	259	0	0
T6	361841	193	0	0
T7	58265	68	0	0
T8	11000	0	0	0
T9	11653	0	0	0
T10	4819	4	0	0
T11	0	4	0	0
T12	0	9	0	0
T13	0	67	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349410	1107	0	0
T5	559463	17	0	0
T6	361841	17	0	0
T7	58265	0	0	0
T8	11000	0	0	0
T9	11653	0	0	0
T10	4819	0	0	0
T11	5139	0	0	0
T12	0	9	0	0
T23	2932	0	0	0
T24	11649	0	0	0
T25	3747	0	0	0
T43	0	9	0	0
T44	0	4	0	0
T45	0	23	0	0
T76	0	14	0	0
T77	0	5	0	0
T78	0	21	0	0
T79	0	8	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349410	13262	0	0
T1	74566	29	0	0
T2	6986	6	0	0
T3	7149	4	0	0
T4	3831	0	0	0
T5	559463	259	0	0
T6	361841	193	0	0
T7	58265	68	0	0
T8	11000	0	0	0
T9	11653	0	0	0
T10	4819	4	0	0
T11	0	4	0	0
T12	0	9	0	0
T13	0	67	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27349410	1107	0	0
T5	559463	17	0	0
T6	361841	17	0	0
T7	58265	0	0	0
T8	11000	0	0	0
T9	11653	0	0	0
T10	4819	0	0	0
T11	5139	0	0	0
T12	0	9	0	0
T23	2932	0	0	0
T24	11649	0	0	0
T25	3747	0	0	0
T43	0	9	0	0
T44	0	4	0	0
T45	0	23	0	0
T76	0	14	0	0
T77	0	5	0	0
T78	0	21	0	0
T79	0	8	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726282	22031	0	0
T1	4727	47	0	0
T2	436	8	0	0
T3	446	6	0	0
T4	239	1	0	0
T5	35439	401	0	0
T6	22994	297	0	0
T7	3656	76	0	0
T8	687	2	0	0
T9	730	2	0	0
T10	299	5	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726282	1190	0	0
T5	35439	12	0	0
T6	22994	16	0	0
T7	3656	0	0	0
T8	687	0	0	0
T9	730	0	0	0
T10	299	0	0	0
T11	321	1	0	0
T12	0	13	0	0
T23	182	0	0	0
T24	729	0	0	0
T25	233	0	0	0
T43	0	12	0	0
T44	0	5	0	0
T45	0	22	0	0
T76	0	12	0	0
T77	0	5	0	0
T78	0	18	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726282	22031	0	0
T1	4727	47	0	0
T2	436	8	0	0
T3	446	6	0	0
T4	239	1	0	0
T5	35439	401	0	0
T6	22994	297	0	0
T7	3656	76	0	0
T8	687	2	0	0
T9	730	2	0	0
T10	299	5	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1726282	1190	0	0
T5	35439	12	0	0
T6	22994	16	0	0
T7	3656	0	0	0
T8	687	0	0	0
T9	730	0	0	0
T10	299	0	0	0
T11	321	1	0	0
T12	0	13	0	0
T23	182	0	0	0
T24	729	0	0	0
T25	233	0	0	0
T43	0	12	0	0
T44	0	5	0	0
T45	0	22	0	0
T76	0	12	0	0
T77	0	5	0	0
T78	0	18	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	14720	0	0
T1	37278	32	0	0
T2	3492	7	0	0
T3	3574	4	0	0
T4	1916	0	0	0
T5	279740	288	0	0
T6	180917	209	0	0
T7	29135	75	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	4	0	0
T11	0	4	0	0
T12	0	12	0	0
T13	0	75	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	1194	0	0
T5	279740	13	0	0
T6	180917	13	0	0
T7	29135	0	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	0	0	0
T11	2568	0	0	0
T12	0	12	0	0
T23	1465	0	0	0
T24	5825	0	0	0
T25	1873	0	0	0
T43	0	11	0	0
T44	0	6	0	0
T45	0	21	0	0
T76	0	11	0	0
T77	0	6	0	0
T78	0	20	0	0
T79	0	13	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	14720	0	0
T1	37278	32	0	0
T2	3492	7	0	0
T3	3574	4	0	0
T4	1916	0	0	0
T5	279740	288	0	0
T6	180917	209	0	0
T7	29135	75	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	4	0	0
T11	0	4	0	0
T12	0	12	0	0
T13	0	75	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	1194	0	0
T5	279740	13	0	0
T6	180917	13	0	0
T7	29135	0	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	0	0	0
T11	2568	0	0	0
T12	0	12	0	0
T23	1465	0	0	0
T24	5825	0	0	0
T25	1873	0	0	0
T43	0	11	0	0
T44	0	6	0	0
T45	0	21	0	0
T76	0	11	0	0
T77	0	6	0	0
T78	0	20	0	0
T79	0	13	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	14807	0	0
T1	37278	32	0	0
T2	3492	7	0	0
T3	3574	4	0	0
T4	1916	0	0	0
T5	279740	289	0	0
T6	180917	212	0	0
T7	29135	75	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	4	0	0
T11	0	4	0	0
T12	0	12	0	0
T13	0	75	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	1288	0	0
T5	279740	17	0	0
T6	180917	16	0	0
T7	29135	0	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	0	0	0
T11	2568	0	0	0
T12	0	12	0	0
T23	1465	0	0	0
T24	5825	0	0	0
T25	1873	0	0	0
T43	0	12	0	0
T44	0	6	0	0
T45	0	23	0	0
T76	0	14	0	0
T77	0	8	0	0
T78	0	21	0	0
T79	0	12	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	14807	0	0
T1	37278	32	0	0
T2	3492	7	0	0
T3	3574	4	0	0
T4	1916	0	0	0
T5	279740	289	0	0
T6	180917	212	0	0
T7	29135	75	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	4	0	0
T11	0	4	0	0
T12	0	12	0	0
T13	0	75	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	1288	0	0
T5	279740	17	0	0
T6	180917	16	0	0
T7	29135	0	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	0	0	0
T11	2568	0	0	0
T12	0	12	0	0
T23	1465	0	0	0
T24	5825	0	0	0
T25	1873	0	0	0
T43	0	12	0	0
T44	0	6	0	0
T45	0	23	0	0
T76	0	14	0	0
T77	0	8	0	0
T78	0	21	0	0
T79	0	12	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	14827	0	0
T1	37278	32	0	0
T2	3492	7	0	0
T3	3574	4	0	0
T4	1916	0	0	0
T5	279740	288	0	0
T6	180917	215	0	0
T7	29135	75	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	4	0	0
T11	0	4	0	0
T12	0	14	0	0
T13	0	75	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	1300	0	0
T5	279740	14	0	0
T6	180917	19	0	0
T7	29135	0	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	0	0	0
T11	2568	0	0	0
T12	0	14	0	0
T23	1465	0	0	0
T24	5825	0	0	0
T25	1873	0	0	0
T43	0	13	0	0
T44	0	8	0	0
T45	0	19	0	0
T76	0	11	0	0
T77	0	9	0	0
T78	0	15	0	0
T79	0	13	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	14827	0	0
T1	37278	32	0	0
T2	3492	7	0	0
T3	3574	4	0	0
T4	1916	0	0	0
T5	279740	288	0	0
T6	180917	215	0	0
T7	29135	75	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	4	0	0
T11	0	4	0	0
T12	0	14	0	0
T13	0	75	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13674448	1300	0	0
T5	279740	14	0	0
T6	180917	19	0	0
T7	29135	0	0	0
T8	5499	0	0	0
T9	5827	0	0	0
T10	2410	0	0	0
T11	2568	0	0	0
T12	0	14	0	0
T23	1465	0	0	0
T24	5825	0	0	0
T25	1873	0	0	0
T43	0	13	0	0
T44	0	8	0	0
T45	0	19	0	0
T76	0	11	0	0
T77	0	9	0	0
T78	0	15	0	0
T79	0	13	0	0