Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12849953	9449	0	0
alert_regwen_rd_A	12849953	6391	0	0
cpu_regwen_rd_A	12849953	6068	0	0
sw_rst_ctrl_n_0_rd_A	12849953	12813	0	0
sw_rst_ctrl_n_1_rd_A	12849953	12495	0	0
sw_rst_ctrl_n_2_rd_A	12849953	12217	0	0
sw_rst_ctrl_n_3_rd_A	12849953	12745	0	0
sw_rst_ctrl_n_4_rd_A	12849953	12431	0	0
sw_rst_ctrl_n_5_rd_A	12849953	12603	0	0
sw_rst_ctrl_n_6_rd_A	12849953	12487	0	0
sw_rst_ctrl_n_7_rd_A	12849953	12646	0	0
sw_rst_regwen_0_rd_A	12849953	6676	0	0
sw_rst_regwen_1_rd_A	12849953	6935	0	0
sw_rst_regwen_2_rd_A	12849953	6901	0	0
sw_rst_regwen_3_rd_A	12849953	6894	0	0
sw_rst_regwen_4_rd_A	12849953	6808	0	0
sw_rst_regwen_5_rd_A	12849953	6924	0	0
sw_rst_regwen_6_rd_A	12849953	6757	0	0
sw_rst_regwen_7_rd_A	12849953	6856	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	9449	0	0
T57	2855	7	0	0
T59	4381	617	0	0
T60	4012	11	0	0
T61	2980	152	0	0
T81	18327	3	0	0
T82	8784	291	0	0
T83	5058	27	0	0
T87	9596	2	0	0
T88	21110	2	0	0
T89	11212	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	6391	0	0
T1	33290	60	0	0
T2	2958	0	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	240	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T46	0	25	0	0
T76	0	187	0	0
T90	0	30	0	0
T91	0	21	0	0
T94	0	57	0	0
T95	0	287	0	0
T100	0	42	0	0
T120	0	64	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	6068	0	0
T1	33290	49	0	0
T2	2958	0	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	212	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T46	0	24	0	0
T76	0	119	0	0
T90	0	10	0	0
T91	0	27	0	0
T94	0	62	0	0
T95	0	272	0	0
T100	0	46	0	0
T120	0	91	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	12813	0	0
T1	33290	38	0	0
T2	2958	26	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	347	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	184	0	0
T44	0	97	0	0
T46	0	21	0	0
T76	0	312	0	0
T90	0	15	0	0
T91	0	48	0	0
T100	0	38	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	12495	0	0
T1	33290	48	0	0
T2	2958	28	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	335	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	197	0	0
T44	0	69	0	0
T46	0	38	0	0
T76	0	247	0	0
T90	0	34	0	0
T91	0	38	0	0
T100	0	46	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	12217	0	0
T1	33290	37	0	0
T2	2958	20	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	322	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	187	0	0
T44	0	70	0	0
T46	0	26	0	0
T76	0	326	0	0
T90	0	11	0	0
T91	0	55	0	0
T100	0	51	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	12745	0	0
T1	33290	43	0	0
T2	2958	18	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	377	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	227	0	0
T44	0	59	0	0
T46	0	23	0	0
T76	0	271	0	0
T90	0	24	0	0
T91	0	61	0	0
T100	0	38	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	12431	0	0
T1	33290	63	0	0
T2	2958	19	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	358	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	188	0	0
T44	0	67	0	0
T46	0	35	0	0
T76	0	279	0	0
T90	0	37	0	0
T91	0	33	0	0
T100	0	46	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	12603	0	0
T1	33290	54	0	0
T2	2958	14	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	290	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	228	0	0
T44	0	69	0	0
T46	0	16	0	0
T76	0	266	0	0
T90	0	24	0	0
T91	0	43	0	0
T100	0	46	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	12487	0	0
T1	33290	33	0	0
T2	2958	16	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	341	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	209	0	0
T44	0	50	0	0
T46	0	22	0	0
T76	0	288	0	0
T90	0	25	0	0
T91	0	20	0	0
T100	0	47	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	12646	0	0
T1	33290	38	0	0
T2	2958	16	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	356	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	203	0	0
T44	0	63	0	0
T46	0	28	0	0
T76	0	256	0	0
T90	0	18	0	0
T91	0	56	0	0
T100	0	47	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	6676	0	0
T1	33290	60	0	0
T2	2958	0	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	211	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	24	0	0
T44	0	15	0	0
T46	0	30	0	0
T76	0	167	0	0
T79	0	36	0	0
T90	0	26	0	0
T91	0	14	0	0
T100	0	31	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	6935	0	0
T1	33290	41	0	0
T2	2958	0	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	246	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	33	0	0
T44	0	19	0	0
T46	0	26	0	0
T76	0	159	0	0
T79	0	46	0	0
T90	0	53	0	0
T91	0	34	0	0
T100	0	41	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	6901	0	0
T1	33290	51	0	0
T2	2958	0	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	229	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	38	0	0
T44	0	26	0	0
T46	0	36	0	0
T76	0	191	0	0
T79	0	37	0	0
T90	0	18	0	0
T91	0	41	0	0
T100	0	50	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	6894	0	0
T1	33290	56	0	0
T2	2958	0	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	239	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	31	0	0
T44	0	13	0	0
T46	0	20	0	0
T76	0	205	0	0
T79	0	38	0	0
T90	0	33	0	0
T91	0	43	0	0
T100	0	47	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	6808	0	0
T1	33290	43	0	0
T2	2958	0	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	155	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	30	0	0
T44	0	46	0	0
T46	0	35	0	0
T76	0	138	0	0
T79	0	25	0	0
T90	0	14	0	0
T91	0	33	0	0
T100	0	51	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	6924	0	0
T1	33290	52	0	0
T2	2958	0	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	153	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	44	0	0
T44	0	11	0	0
T46	0	32	0	0
T76	0	167	0	0
T79	0	22	0	0
T90	0	36	0	0
T91	0	15	0	0
T100	0	40	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	6757	0	0
T1	33290	50	0	0
T2	2958	0	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	218	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	33	0	0
T44	0	13	0	0
T46	0	24	0	0
T76	0	175	0	0
T79	0	39	0	0
T90	0	11	0	0
T91	0	38	0	0
T100	0	49	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12849953	6856	0	0
T1	33290	48	0	0
T2	2958	0	0	0
T3	3332	0	0	0
T4	1897	0	0	0
T5	246979	192	0	0
T6	157677	0	0	0
T7	25957	0	0	0
T8	5385	0	0	0
T9	5092	0	0	0
T10	2118	0	0	0
T43	0	37	0	0
T44	0	11	0	0
T46	0	42	0	0
T76	0	146	0	0
T79	0	26	0	0
T90	0	8	0	0
T91	0	25	0	0
T100	0	61	0	0