Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	653015	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

391229

1

T1

5

T3

5

T5

1185

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	559229	1			T4	1		T5	1694		T6	1500
values[0x0]	241798	1			T1	11		T3	7		T5	654
values[0x1]	243217	1			T1	12		T3	9		T5	659

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	547422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

496822

1

T1

6

T3

7

T5

1484

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4093	1			T5	20		T6	17		T7	18
valid_sources[0x01]	3174	1			T5	13		T6	4		T7	7
valid_sources[0x02]	4715	1			T5	10		T6	15		T7	18
valid_sources[0x03]	4662	1			T5	6		T6	6		T7	13
valid_sources[0x04]	3809	1			T5	13		T6	16		T7	8
valid_sources[0x05]	4303	1			T5	15		T6	4		T7	11
valid_sources[0x06]	5063	1			T5	16		T6	24		T7	9
valid_sources[0x07]	3373	1			T5	12		T6	7		T7	10
valid_sources[0x08]	3853	1			T1	1		T5	8		T6	22
valid_sources[0x09]	5660	1			T5	18		T6	11		T7	12
valid_sources[0x0a]	3708	1			T5	4		T6	10		T7	6
valid_sources[0x0b]	5046	1			T5	10		T6	3		T7	13
valid_sources[0x0c]	3589	1			T1	1		T5	7		T6	9
valid_sources[0x0d]	3860	1			T5	8		T6	7		T7	16
valid_sources[0x0e]	3315	1			T5	12		T6	15		T7	22
valid_sources[0x0f]	3459	1			T5	19		T6	11		T7	15
valid_sources[0x10]	3767	1			T5	13		T6	20		T7	9
valid_sources[0x11]	3143	1			T5	8		T6	26		T7	7
valid_sources[0x12]	3794	1			T5	17		T6	5		T7	7
valid_sources[0x13]	3725	1			T5	13		T6	22		T7	22
valid_sources[0x14]	3238	1			T5	15		T6	24		T7	15
valid_sources[0x15]	5038	1			T5	9		T6	4		T7	24
valid_sources[0x16]	3252	1			T5	14		T6	3		T7	11
valid_sources[0x17]	3365	1			T5	12		T6	4		T7	12
valid_sources[0x18]	9975	1			T5	8		T7	7		T8	5
valid_sources[0x19]	3626	1			T5	8		T6	32		T7	13
valid_sources[0x1a]	4626	1			T1	1		T5	13		T6	20
valid_sources[0x1b]	4039	1			T5	11		T6	22		T7	9
valid_sources[0x1c]	3822	1			T5	12		T6	33		T7	19
valid_sources[0x1d]	3521	1			T5	10		T6	7		T7	23
valid_sources[0x1e]	3955	1			T5	7		T6	12		T7	19
valid_sources[0x1f]	5113	1			T5	9		T6	42		T7	15
valid_sources[0x20]	4713	1			T5	13		T6	15		T7	18
valid_sources[0x21]	4439	1			T5	8		T6	13		T7	15
valid_sources[0x22]	4540	1			T5	13		T6	29		T7	16
valid_sources[0x23]	3496	1			T5	14		T6	15		T7	8
valid_sources[0x24]	3300	1			T5	14		T7	11		T8	9
valid_sources[0x25]	4685	1			T5	9		T6	10		T7	8
valid_sources[0x26]	3178	1			T5	10		T6	3		T7	11
valid_sources[0x27]	3661	1			T5	18		T6	14		T7	15
valid_sources[0x28]	3360	1			T5	12		T6	5		T7	9
valid_sources[0x29]	3619	1			T5	12		T6	26		T7	8
valid_sources[0x2a]	3560	1			T5	8		T6	6		T7	17
valid_sources[0x2b]	3895	1			T5	14		T6	10		T7	13
valid_sources[0x2c]	4073	1			T5	8		T6	7		T7	11
valid_sources[0x2d]	3604	1			T5	10		T6	26		T7	16
valid_sources[0x2e]	4227	1			T5	19		T6	21		T7	17
valid_sources[0x2f]	4793	1			T5	13		T6	8		T7	16
valid_sources[0x30]	5268	1			T5	5		T6	20		T7	14
valid_sources[0x31]	3504	1			T5	16		T6	10		T7	21
valid_sources[0x32]	3121	1			T5	10		T6	17		T7	4
valid_sources[0x33]	4297	1			T5	9		T6	4		T7	13
valid_sources[0x34]	3518	1			T5	10		T6	8		T7	11
valid_sources[0x35]	3656	1			T5	13		T6	5		T7	9
valid_sources[0x36]	4371	1			T5	12		T6	9		T7	15
valid_sources[0x37]	3512	1			T5	9		T6	19		T7	10
valid_sources[0x38]	3885	1			T5	13		T6	16		T7	6
valid_sources[0x39]	3731	1			T5	14		T6	23		T7	10
valid_sources[0x3a]	3879	1			T5	8		T6	3		T7	11
valid_sources[0x3b]	4327	1			T1	1		T5	12		T6	6
valid_sources[0x3c]	3656	1			T5	8		T6	6		T7	15
valid_sources[0x3d]	3313	1			T5	16		T6	23		T7	8
valid_sources[0x3e]	3842	1			T5	5		T6	15		T7	14
valid_sources[0x3f]	4466	1			T1	1		T5	18		T6	27
valid_sources[0x40]	4729	1			T5	11		T6	10		T7	12
valid_sources[0x41]	3106	1			T5	9		T6	3		T7	9
valid_sources[0x42]	4557	1			T5	13		T6	3		T7	8
valid_sources[0x43]	4011	1			T5	26		T6	3		T7	11
valid_sources[0x44]	3120	1			T5	17		T6	10		T7	11
valid_sources[0x45]	4248	1			T5	11		T7	21		T8	9
valid_sources[0x46]	3825	1			T5	13		T6	10		T7	15
valid_sources[0x47]	3733	1			T5	13		T6	8		T7	13
valid_sources[0x48]	3273	1			T5	6		T6	4		T7	9
valid_sources[0x49]	3591	1			T5	9		T6	26		T7	15
valid_sources[0x4a]	4683	1			T5	11		T6	41		T7	9
valid_sources[0x4b]	3837	1			T5	13		T6	18		T7	13
valid_sources[0x4c]	4244	1			T5	11		T6	29		T7	8
valid_sources[0x4d]	4623	1			T5	11		T6	21		T7	9
valid_sources[0x4e]	3596	1			T5	10		T6	24		T7	5
valid_sources[0x4f]	3620	1			T5	14		T6	21		T7	6
valid_sources[0x50]	3856	1			T5	13		T6	11		T7	19
valid_sources[0x51]	4748	1			T5	7		T6	9		T7	11
valid_sources[0x52]	4191	1			T5	9		T6	7		T7	15
valid_sources[0x53]	4747	1			T5	8		T6	5		T7	12
valid_sources[0x54]	3694	1			T5	17		T6	21		T7	7
valid_sources[0x55]	3535	1			T5	6		T6	5		T7	23
valid_sources[0x56]	4164	1			T5	12		T6	15		T7	21
valid_sources[0x57]	4043	1			T5	5		T6	12		T7	16
valid_sources[0x58]	5280	1			T5	7		T6	7		T7	18
valid_sources[0x59]	3633	1			T5	14		T6	15		T7	16
valid_sources[0x5a]	3163	1			T5	13		T6	6		T7	14
valid_sources[0x5b]	4610	1			T5	17		T6	12		T7	6
valid_sources[0x5c]	5655	1			T5	22		T6	14		T7	20
valid_sources[0x5d]	3218	1			T1	2		T5	12		T6	1
valid_sources[0x5e]	3588	1			T5	18		T6	8		T7	10
valid_sources[0x5f]	3380	1			T5	8		T6	4		T7	12
valid_sources[0x60]	3501	1			T5	9		T6	3		T7	3
valid_sources[0x61]	3736	1			T1	1		T5	15		T6	10
valid_sources[0x62]	4188	1			T5	9		T6	27		T7	8
valid_sources[0x63]	3510	1			T5	22		T6	15		T7	11
valid_sources[0x64]	3711	1			T3	1		T5	15		T7	13
valid_sources[0x65]	4879	1			T5	16		T6	22		T7	20
valid_sources[0x66]	3637	1			T5	15		T6	11		T7	16
valid_sources[0x67]	3312	1			T5	12		T6	13		T7	20
valid_sources[0x68]	3175	1			T5	14		T6	15		T7	12
valid_sources[0x69]	3782	1			T5	10		T6	19		T7	10
valid_sources[0x6a]	3091	1			T5	8		T6	4		T7	10
valid_sources[0x6b]	3541	1			T5	13		T6	14		T7	19
valid_sources[0x6c]	4309	1			T5	14		T6	20		T7	15
valid_sources[0x6d]	4575	1			T5	5		T6	7		T7	14
valid_sources[0x6e]	3496	1			T5	15		T6	16		T7	15
valid_sources[0x6f]	3858	1			T5	17		T6	10		T7	18
valid_sources[0x70]	3161	1			T5	12		T6	16		T7	17
valid_sources[0x71]	3087	1			T5	15		T7	9		T8	11
valid_sources[0x72]	3549	1			T5	13		T6	11		T7	16
valid_sources[0x73]	4686	1			T5	7		T6	7		T7	16
valid_sources[0x74]	5038	1			T5	8		T6	14		T7	11
valid_sources[0x75]	3949	1			T5	19		T6	2		T7	13
valid_sources[0x76]	4731	1			T5	17		T6	17		T7	11
valid_sources[0x77]	4246	1			T5	3		T6	47		T7	17
valid_sources[0x78]	5008	1			T3	8		T5	10		T6	19
valid_sources[0x79]	3543	1			T5	12		T6	12		T7	14
valid_sources[0x7a]	3748	1			T5	17		T6	8		T7	6
valid_sources[0x7b]	3637	1			T4	1		T5	14		T6	3
valid_sources[0x7c]	7414	1			T5	8		T6	4		T7	13
valid_sources[0x7d]	3943	1			T5	11		T6	3		T7	10
valid_sources[0x7e]	3645	1			T1	1		T5	11		T6	9
valid_sources[0x7f]	5142	1			T5	10		T6	7		T7	15
valid_sources[0x80]	7875	1			T5	12		T6	36		T7	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

261375

1

T5

841

T6

692

T7

794

values[0x0]

all_enables

biggest_size

84413

1

T1

3

T3

2

T5

227

values[0x1]

all_enables

biggest_size

45441

1

T1

2

T3

3

T5

117