Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T7,T8

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55074891	9353	0	0
CascadeEffAonToRstPorAboveRise_A	55074891	9353	0	0
CascadeEffAonToRstPorIoAboveFall_A	52871073	9353	0	0
CascadeEffAonToRstPorIoAboveRise_A	52871073	9353	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26436174	9353	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26436174	9353	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13217912	9353	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13217912	9353	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26436222	9353	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26436222	9353	0	0
CascadeLcToLcAboveFall_A	55074891	23280	0	0
CascadeLcToLcAboveRise_A	55074891	23280	0	0
CascadeLcToLcAonAboveFall_A	1670361	23280	0	0
CascadeLcToLcAonAboveRise_A	1670361	23280	0	0
CascadeLcToLcShadowedAboveFall_A	55074891	23280	0	0
CascadeLcToLcShadowedAboveRise_A	55074891	23280	0	0
CascadePorToAonAboveFall_A	1670361	7313	0	0
CascadeSysToSysAboveFall_A	55074891	23280	0	0
CascadeSysToSysAboveRise_A	55074891	23280	0	0
ScanRstToAonRise_A	1670361	278	0	0
StablePorToAonRise_A	1670361	9353	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11564874	23280	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11564874	23280	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11564874	23280	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11564874	23280	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13217912	23280	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13217912	23280	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11564874	23280	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11564874	23280	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11564874	23280	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11564874	23280	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55074891	9353	0	0
T1	6690	1	0	0
T2	24371	8	0	0
T3	6110	1	0	0
T4	17581	2	0	0
T5	96182	21	0	0
T6	123322	27	0	0
T7	221392	20	0	0
T8	73370	16	0	0
T9	6418	1	0	0
T10	91040	21	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55074891	9353	0	0
T1	6690	1	0	0
T2	24371	8	0	0
T3	6110	1	0	0
T4	17581	2	0	0
T5	96182	21	0	0
T6	123322	27	0	0
T7	221392	20	0	0
T8	73370	16	0	0
T9	6418	1	0	0
T10	91040	21	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871073	9353	0	0
T1	6422	1	0	0
T2	23391	8	0	0
T3	5866	1	0	0
T4	16877	2	0	0
T5	92323	21	0	0
T6	118398	27	0	0
T7	212513	20	0	0
T8	70440	16	0	0
T9	6161	1	0	0
T10	87376	21	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871073	9353	0	0
T1	6422	1	0	0
T2	23391	8	0	0
T3	5866	1	0	0
T4	16877	2	0	0
T5	92323	21	0	0
T6	118398	27	0	0
T7	212513	20	0	0
T8	70440	16	0	0
T9	6161	1	0	0
T10	87376	21	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436174	9353	0	0
T1	3212	1	0	0
T2	11703	8	0	0
T3	2934	1	0	0
T4	8438	2	0	0
T5	46164	21	0	0
T6	59190	27	0	0
T7	106265	20	0	0
T8	35216	16	0	0
T9	3080	1	0	0
T10	43697	21	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436174	9353	0	0
T1	3212	1	0	0
T2	11703	8	0	0
T3	2934	1	0	0
T4	8438	2	0	0
T5	46164	21	0	0
T6	59190	27	0	0
T7	106265	20	0	0
T8	35216	16	0	0
T9	3080	1	0	0
T10	43697	21	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	9353	0	0
T1	1604	1	0	0
T2	5850	8	0	0
T3	1466	1	0	0
T4	4217	2	0	0
T5	23075	21	0	0
T6	29607	27	0	0
T7	53129	20	0	0
T8	17607	16	0	0
T9	1539	1	0	0
T10	21856	21	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	9353	0	0
T1	1604	1	0	0
T2	5850	8	0	0
T3	1466	1	0	0
T4	4217	2	0	0
T5	23075	21	0	0
T6	29607	27	0	0
T7	53129	20	0	0
T8	17607	16	0	0
T9	1539	1	0	0
T10	21856	21	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436222	9353	0	0
T1	3211	1	0	0
T2	11691	8	0	0
T3	2933	1	0	0
T4	8438	2	0	0
T5	46168	21	0	0
T6	59185	27	0	0
T7	106272	20	0	0
T8	35226	16	0	0
T9	3080	1	0	0
T10	43696	21	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436222	9353	0	0
T1	3211	1	0	0
T2	11691	8	0	0
T3	2933	1	0	0
T4	8438	2	0	0
T5	46168	21	0	0
T6	59185	27	0	0
T7	106272	20	0	0
T8	35226	16	0	0
T9	3080	1	0	0
T10	43696	21	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55074891	23280	0	0
T1	6690	1	0	0
T2	24371	8	0	0
T3	6110	1	0	0
T4	17581	2	0	0
T5	96182	59	0	0
T6	123322	102	0	0
T7	221392	60	0	0
T8	73370	47	0	0
T9	6418	1	0	0
T10	91040	51	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55074891	23280	0	0
T1	6690	1	0	0
T2	24371	8	0	0
T3	6110	1	0	0
T4	17581	2	0	0
T5	96182	59	0	0
T6	123322	102	0	0
T7	221392	60	0	0
T8	73370	47	0	0
T9	6418	1	0	0
T10	91040	51	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670361	23280	0	0
T1	200	1	0	0
T2	732	8	0	0
T3	183	1	0	0
T4	526	2	0	0
T5	2974	59	0	0
T6	3715	102	0	0
T7	6702	60	0	0
T8	2243	47	0	0
T9	191	1	0	0
T10	2789	51	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670361	23280	0	0
T1	200	1	0	0
T2	732	8	0	0
T3	183	1	0	0
T4	526	2	0	0
T5	2974	59	0	0
T6	3715	102	0	0
T7	6702	60	0	0
T8	2243	47	0	0
T9	191	1	0	0
T10	2789	51	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55074891	23280	0	0
T1	6690	1	0	0
T2	24371	8	0	0
T3	6110	1	0	0
T4	17581	2	0	0
T5	96182	59	0	0
T6	123322	102	0	0
T7	221392	60	0	0
T8	73370	47	0	0
T9	6418	1	0	0
T10	91040	51	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55074891	23280	0	0
T1	6690	1	0	0
T2	24371	8	0	0
T3	6110	1	0	0
T4	17581	2	0	0
T5	96182	59	0	0
T6	123322	102	0	0
T7	221392	60	0	0
T8	73370	47	0	0
T9	6418	1	0	0
T10	91040	51	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670361	7313	0	0
T1	200	1	0	0
T2	732	8	0	0
T3	183	1	0	0
T4	526	20	0	0
T5	2974	10	0	0
T6	3715	27	0	0
T7	6702	9	0	0
T8	2243	8	0	0
T9	191	1	0	0
T10	2789	9	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55074891	23280	0	0
T1	6690	1	0	0
T2	24371	8	0	0
T3	6110	1	0	0
T4	17581	2	0	0
T5	96182	59	0	0
T6	123322	102	0	0
T7	221392	60	0	0
T8	73370	47	0	0
T9	6418	1	0	0
T10	91040	51	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55074891	23280	0	0
T1	6690	1	0	0
T2	24371	8	0	0
T3	6110	1	0	0
T4	17581	2	0	0
T5	96182	59	0	0
T6	123322	102	0	0
T7	221392	60	0	0
T8	73370	47	0	0
T9	6418	1	0	0
T10	91040	51	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670361	278	0	0
T7	6702	1	0	0
T8	2243	1	0	0
T9	191	0	0	0
T10	2789	0	0	0
T11	467	0	0	0
T12	421	0	0	0
T13	230	0	0	0
T14	3471	2	0	0
T26	732	0	0	0
T42	0	2	0	0
T50	746	0	0	0
T80	0	4	0	0
T83	0	8	0	0
T88	0	4	0	0
T90	0	1	0	0
T91	0	6	0	0
T103	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670361	9353	0	0
T1	200	1	0	0
T2	732	8	0	0
T3	183	1	0	0
T4	526	2	0	0
T5	2974	21	0	0
T6	3715	27	0	0
T7	6702	20	0	0
T8	2243	16	0	0
T9	191	1	0	0
T10	2789	21	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564874	23280	0	0
T1	1586	1	0	0
T2	5302	8	0	0
T3	1423	1	0	0
T4	4128	2	0	0
T5	17948	59	0	0
T6	26119	102	0	0
T7	48623	60	0	0
T8	14110	47	0	0
T9	1521	1	0	0
T10	16381	51	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564874	23280	0	0
T1	1586	1	0	0
T2	5302	8	0	0
T3	1423	1	0	0
T4	4128	2	0	0
T5	17948	59	0	0
T6	26119	102	0	0
T7	48623	60	0	0
T8	14110	47	0	0
T9	1521	1	0	0
T10	16381	51	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564874	23280	0	0
T1	1586	1	0	0
T2	5302	8	0	0
T3	1423	1	0	0
T4	4128	2	0	0
T5	17948	59	0	0
T6	26119	102	0	0
T7	48623	60	0	0
T8	14110	47	0	0
T9	1521	1	0	0
T10	16381	51	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564874	23280	0	0
T1	1586	1	0	0
T2	5302	8	0	0
T3	1423	1	0	0
T4	4128	2	0	0
T5	17948	59	0	0
T6	26119	102	0	0
T7	48623	60	0	0
T8	14110	47	0	0
T9	1521	1	0	0
T10	16381	51	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	23280	0	0
T1	1604	1	0	0
T2	5850	8	0	0
T3	1466	1	0	0
T4	4217	2	0	0
T5	23075	59	0	0
T6	29607	102	0	0
T7	53129	60	0	0
T8	17607	47	0	0
T9	1539	1	0	0
T10	21856	51	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	23280	0	0
T1	1604	1	0	0
T2	5850	8	0	0
T3	1466	1	0	0
T4	4217	2	0	0
T5	23075	59	0	0
T6	29607	102	0	0
T7	53129	60	0	0
T8	17607	47	0	0
T9	1539	1	0	0
T10	21856	51	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564874	23280	0	0
T1	1586	1	0	0
T2	5302	8	0	0
T3	1423	1	0	0
T4	4128	2	0	0
T5	17948	59	0	0
T6	26119	102	0	0
T7	48623	60	0	0
T8	14110	47	0	0
T9	1521	1	0	0
T10	16381	51	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564874	23280	0	0
T1	1586	1	0	0
T2	5302	8	0	0
T3	1423	1	0	0
T4	4128	2	0	0
T5	17948	59	0	0
T6	26119	102	0	0
T7	48623	60	0	0
T8	14110	47	0	0
T9	1521	1	0	0
T10	16381	51	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564874	23280	0	0
T1	1586	1	0	0
T2	5302	8	0	0
T3	1423	1	0	0
T4	4128	2	0	0
T5	17948	59	0	0
T6	26119	102	0	0
T7	48623	60	0	0
T8	14110	47	0	0
T9	1521	1	0	0
T10	16381	51	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564874	23280	0	0
T1	1586	1	0	0
T2	5302	8	0	0
T3	1423	1	0	0
T4	4128	2	0	0
T5	17948	59	0	0
T6	26119	102	0	0
T7	48623	60	0	0
T8	14110	47	0	0
T9	1521	1	0	0
T10	16381	51	0	0