Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T50
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T50
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T50
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T50
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T50
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T50
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T50
1	0	Covered	T2,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T50
1	0	Covered	T2,T4,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13217912	14759	0	0
gen_assertions[0].RstEnOn_A	13217912	1004	0	0
gen_assertions[0].RstNOff_A	13217912	14759	0	0
gen_assertions[0].RstNOn_A	13217912	1004	0	0
gen_assertions[1].RstEnOff_A	52871073	13423	0	0
gen_assertions[1].RstEnOn_A	52871073	988	0	0
gen_assertions[1].RstNOff_A	52871073	13423	0	0
gen_assertions[1].RstNOn_A	52871073	988	0	0
gen_assertions[2].RstEnOff_A	26436174	13484	0	0
gen_assertions[2].RstEnOn_A	26436174	993	0	0
gen_assertions[2].RstNOff_A	26436174	13484	0	0
gen_assertions[2].RstNOn_A	26436174	993	0	0
gen_assertions[3].RstEnOff_A	26436222	13507	0	0
gen_assertions[3].RstEnOn_A	26436222	1009	0	0
gen_assertions[3].RstNOff_A	26436222	13507	0	0
gen_assertions[3].RstNOn_A	26436222	1009	0	0
gen_assertions[4].RstEnOff_A	1670361	23012	0	0
gen_assertions[4].RstEnOn_A	1670361	1083	0	0
gen_assertions[4].RstNOff_A	1670361	23012	0	0
gen_assertions[4].RstNOn_A	1670361	1083	0	0
gen_assertions[5].RstEnOff_A	13217912	15028	0	0
gen_assertions[5].RstEnOn_A	13217912	1141	0	0
gen_assertions[5].RstNOff_A	13217912	15028	0	0
gen_assertions[5].RstNOn_A	13217912	1141	0	0
gen_assertions[6].RstEnOff_A	13217912	15067	0	0
gen_assertions[6].RstEnOn_A	13217912	1169	0	0
gen_assertions[6].RstNOff_A	13217912	15067	0	0
gen_assertions[6].RstNOn_A	13217912	1169	0	0
gen_assertions[7].RstEnOff_A	13217912	15097	0	0
gen_assertions[7].RstEnOn_A	13217912	1207	0	0
gen_assertions[7].RstNOff_A	13217912	15097	0	0
gen_assertions[7].RstNOn_A	13217912	1207	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	14759	0	0
T5	23075	38	0	0
T6	29607	75	0	0
T7	53129	45	0	0
T8	17607	31	0	0
T9	1539	0	0	0
T10	21856	30	0	0
T11	3750	7	0	0
T12	3377	4	0	0
T13	1850	1	0	0
T14	27219	33	0	0
T50	0	1	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	1004	0	0
T7	53129	5	0	0
T8	17607	0	0	0
T9	1539	0	0	0
T10	21856	0	0	0
T11	3750	7	0	0
T12	3377	0	0	0
T13	1850	0	0	0
T14	27219	0	0	0
T26	5835	0	0	0
T37	0	4	0	0
T38	0	1	0	0
T50	5972	1	0	0
T85	0	7	0	0
T86	0	1	0	0
T87	0	5	0	0
T88	0	18	0	0
T89	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	14759	0	0
T5	23075	38	0	0
T6	29607	75	0	0
T7	53129	45	0	0
T8	17607	31	0	0
T9	1539	0	0	0
T10	21856	30	0	0
T11	3750	7	0	0
T12	3377	4	0	0
T13	1850	1	0	0
T14	27219	33	0	0
T50	0	1	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	1004	0	0
T7	53129	5	0	0
T8	17607	0	0	0
T9	1539	0	0	0
T10	21856	0	0	0
T11	3750	7	0	0
T12	3377	0	0	0
T13	1850	0	0	0
T14	27219	0	0	0
T26	5835	0	0	0
T37	0	4	0	0
T38	0	1	0	0
T50	5972	1	0	0
T85	0	7	0	0
T86	0	1	0	0
T87	0	5	0	0
T88	0	18	0	0
T89	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871073	13423	0	0
T5	92323	35	0	0
T6	118398	67	0	0
T7	212513	43	0	0
T8	70440	28	0	0
T9	6161	0	0	0
T10	87376	28	0	0
T11	15008	7	0	0
T12	13509	3	0	0
T13	7403	1	0	0
T14	108843	26	0	0
T50	0	1	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871073	988	0	0
T7	212513	7	0	0
T8	70440	0	0	0
T9	6161	0	0	0
T10	87376	0	0	0
T11	15008	7	0	0
T12	13509	0	0	0
T13	7403	0	0	0
T14	108843	0	0	0
T26	23344	0	0	0
T37	0	5	0	0
T50	23892	1	0	0
T85	0	2	0	0
T86	0	1	0	0
T87	0	7	0	0
T88	0	19	0	0
T90	0	1	0	0
T91	0	26	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871073	13423	0	0
T5	92323	35	0	0
T6	118398	67	0	0
T7	212513	43	0	0
T8	70440	28	0	0
T9	6161	0	0	0
T10	87376	28	0	0
T11	15008	7	0	0
T12	13509	3	0	0
T13	7403	1	0	0
T14	108843	26	0	0
T50	0	1	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52871073	988	0	0
T7	212513	7	0	0
T8	70440	0	0	0
T9	6161	0	0	0
T10	87376	0	0	0
T11	15008	7	0	0
T12	13509	0	0	0
T13	7403	0	0	0
T14	108843	0	0	0
T26	23344	0	0	0
T37	0	5	0	0
T50	23892	1	0	0
T85	0	2	0	0
T86	0	1	0	0
T87	0	7	0	0
T88	0	19	0	0
T90	0	1	0	0
T91	0	26	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436174	13484	0	0
T5	46164	35	0	0
T6	59190	67	0	0
T7	106265	45	0	0
T8	35216	28	0	0
T9	3080	0	0	0
T10	43697	28	0	0
T11	7504	11	0	0
T12	6754	3	0	0
T13	3701	1	0	0
T14	54431	26	0	0
T50	0	3	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436174	993	0	0
T7	106265	9	0	0
T8	35216	0	0	0
T9	3080	0	0	0
T10	43697	0	0	0
T11	7504	11	0	0
T12	6754	0	0	0
T13	3701	0	0	0
T14	54431	0	0	0
T26	11674	0	0	0
T37	0	7	0	0
T50	11946	3	0	0
T79	0	5	0	0
T85	0	2	0	0
T87	0	5	0	0
T88	0	19	0	0
T90	0	1	0	0
T91	0	21	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436174	13484	0	0
T5	46164	35	0	0
T6	59190	67	0	0
T7	106265	45	0	0
T8	35216	28	0	0
T9	3080	0	0	0
T10	43697	28	0	0
T11	7504	11	0	0
T12	6754	3	0	0
T13	3701	1	0	0
T14	54431	26	0	0
T50	0	3	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436174	993	0	0
T7	106265	9	0	0
T8	35216	0	0	0
T9	3080	0	0	0
T10	43697	0	0	0
T11	7504	11	0	0
T12	6754	0	0	0
T13	3701	0	0	0
T14	54431	0	0	0
T26	11674	0	0	0
T37	0	7	0	0
T50	11946	3	0	0
T79	0	5	0	0
T85	0	2	0	0
T87	0	5	0	0
T88	0	19	0	0
T90	0	1	0	0
T91	0	21	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436222	13507	0	0
T5	46168	35	0	0
T6	59185	67	0	0
T7	106272	43	0	0
T8	35226	28	0	0
T9	3080	0	0	0
T10	43696	28	0	0
T11	7504	10	0	0
T12	6753	3	0	0
T13	3701	1	0	0
T14	54424	26	0	0
T50	0	3	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436222	1009	0	0
T7	106272	7	0	0
T8	35226	0	0	0
T9	3080	0	0	0
T10	43696	0	0	0
T11	7504	10	0	0
T12	6753	0	0	0
T13	3701	0	0	0
T14	54424	0	0	0
T26	11673	0	0	0
T37	0	7	0	0
T50	11946	3	0	0
T65	0	13	0	0
T79	0	6	0	0
T83	0	35	0	0
T87	0	9	0	0
T88	0	15	0	0
T91	0	21	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436222	13507	0	0
T5	46168	35	0	0
T6	59185	67	0	0
T7	106272	43	0	0
T8	35226	28	0	0
T9	3080	0	0	0
T10	43696	28	0	0
T11	7504	10	0	0
T12	6753	3	0	0
T13	3701	1	0	0
T14	54424	26	0	0
T50	0	3	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26436222	1009	0	0
T7	106272	7	0	0
T8	35226	0	0	0
T9	3080	0	0	0
T10	43696	0	0	0
T11	7504	10	0	0
T12	6753	0	0	0
T13	3701	0	0	0
T14	54424	0	0	0
T26	11673	0	0	0
T37	0	7	0	0
T50	11946	3	0	0
T65	0	13	0	0
T79	0	6	0	0
T83	0	35	0	0
T87	0	9	0	0
T88	0	15	0	0
T91	0	21	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670361	23012	0	0
T1	200	1	0	0
T2	732	2	0	0
T3	183	1	0	0
T4	526	2	0	0
T5	2974	59	0	0
T6	3715	76	0	0
T7	6702	67	0	0
T8	2243	47	0	0
T9	191	1	0	0
T10	2789	51	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670361	1083	0	0
T7	6702	8	0	0
T8	2243	0	0	0
T9	191	0	0	0
T10	2789	0	0	0
T11	467	11	0	0
T12	421	0	0	0
T13	230	0	0	0
T14	3471	0	0	0
T26	732	0	0	0
T37	0	10	0	0
T50	746	4	0	0
T79	0	8	0	0
T82	0	1	0	0
T87	0	8	0	0
T88	0	18	0	0
T90	0	1	0	0
T91	0	21	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670361	23012	0	0
T1	200	1	0	0
T2	732	2	0	0
T3	183	1	0	0
T4	526	2	0	0
T5	2974	59	0	0
T6	3715	76	0	0
T7	6702	67	0	0
T8	2243	47	0	0
T9	191	1	0	0
T10	2789	51	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1670361	1083	0	0
T7	6702	8	0	0
T8	2243	0	0	0
T9	191	0	0	0
T10	2789	0	0	0
T11	467	11	0	0
T12	421	0	0	0
T13	230	0	0	0
T14	3471	0	0	0
T26	732	0	0	0
T37	0	10	0	0
T50	746	4	0	0
T79	0	8	0	0
T82	0	1	0	0
T87	0	8	0	0
T88	0	18	0	0
T90	0	1	0	0
T91	0	21	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	15028	0	0
T5	23075	38	0	0
T6	29607	75	0	0
T7	53129	47	0	0
T8	17607	31	0	0
T9	1539	0	0	0
T10	21856	30	0	0
T11	3750	12	0	0
T12	3377	4	0	0
T13	1850	1	0	0
T14	27219	33	0	0
T50	0	6	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	1141	0	0
T7	53129	9	0	0
T8	17607	0	0	0
T9	1539	0	0	0
T10	21856	0	0	0
T11	3750	12	0	0
T12	3377	0	0	0
T13	1850	0	0	0
T14	27219	0	0	0
T26	5835	0	0	0
T37	0	12	0	0
T50	5972	6	0	0
T65	0	15	0	0
T79	0	10	0	0
T83	0	37	0	0
T87	0	9	0	0
T88	0	18	0	0
T91	0	24	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	15028	0	0
T5	23075	38	0	0
T6	29607	75	0	0
T7	53129	47	0	0
T8	17607	31	0	0
T9	1539	0	0	0
T10	21856	30	0	0
T11	3750	12	0	0
T12	3377	4	0	0
T13	1850	1	0	0
T14	27219	33	0	0
T50	0	6	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	1141	0	0
T7	53129	9	0	0
T8	17607	0	0	0
T9	1539	0	0	0
T10	21856	0	0	0
T11	3750	12	0	0
T12	3377	0	0	0
T13	1850	0	0	0
T14	27219	0	0	0
T26	5835	0	0	0
T37	0	12	0	0
T50	5972	6	0	0
T65	0	15	0	0
T79	0	10	0	0
T83	0	37	0	0
T87	0	9	0	0
T88	0	18	0	0
T91	0	24	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	15067	0	0
T5	23075	38	0	0
T6	29607	75	0	0
T7	53129	47	0	0
T8	17607	31	0	0
T9	1539	0	0	0
T10	21856	30	0	0
T11	3750	12	0	0
T12	3377	4	0	0
T13	1850	1	0	0
T14	27219	33	0	0
T50	0	6	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	1169	0	0
T7	53129	7	0	0
T8	17607	0	0	0
T9	1539	0	0	0
T10	21856	0	0	0
T11	3750	12	0	0
T12	3377	0	0	0
T13	1850	0	0	0
T14	27219	0	0	0
T26	5835	0	0	0
T37	0	12	0	0
T50	5972	6	0	0
T79	0	11	0	0
T83	0	37	0	0
T87	0	10	0	0
T88	0	17	0	0
T90	0	1	0	0
T91	0	21	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	15067	0	0
T5	23075	38	0	0
T6	29607	75	0	0
T7	53129	47	0	0
T8	17607	31	0	0
T9	1539	0	0	0
T10	21856	30	0	0
T11	3750	12	0	0
T12	3377	4	0	0
T13	1850	1	0	0
T14	27219	33	0	0
T50	0	6	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	1169	0	0
T7	53129	7	0	0
T8	17607	0	0	0
T9	1539	0	0	0
T10	21856	0	0	0
T11	3750	12	0	0
T12	3377	0	0	0
T13	1850	0	0	0
T14	27219	0	0	0
T26	5835	0	0	0
T37	0	12	0	0
T50	5972	6	0	0
T79	0	11	0	0
T83	0	37	0	0
T87	0	10	0	0
T88	0	17	0	0
T90	0	1	0	0
T91	0	21	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	15097	0	0
T5	23075	38	0	0
T6	29607	75	0	0
T7	53129	46	0	0
T8	17607	31	0	0
T9	1539	0	0	0
T10	21856	30	0	0
T11	3750	15	0	0
T12	3377	4	0	0
T13	1850	1	0	0
T14	27219	33	0	0
T50	0	8	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	1207	0	0
T7	53129	6	0	0
T8	17607	0	0	0
T9	1539	0	0	0
T10	21856	0	0	0
T11	3750	15	0	0
T12	3377	0	0	0
T13	1850	0	0	0
T14	27219	0	0	0
T26	5835	0	0	0
T37	0	14	0	0
T50	5972	8	0	0
T79	0	10	0	0
T83	0	30	0	0
T87	0	12	0	0
T88	0	22	0	0
T90	0	1	0	0
T91	0	23	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	15097	0	0
T5	23075	38	0	0
T6	29607	75	0	0
T7	53129	46	0	0
T8	17607	31	0	0
T9	1539	0	0	0
T10	21856	30	0	0
T11	3750	15	0	0
T12	3377	4	0	0
T13	1850	1	0	0
T14	27219	33	0	0
T50	0	8	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13217912	1207	0	0
T7	53129	6	0	0
T8	17607	0	0	0
T9	1539	0	0	0
T10	21856	0	0	0
T11	3750	15	0	0
T12	3377	0	0	0
T13	1850	0	0	0
T14	27219	0	0	0
T26	5835	0	0	0
T37	0	14	0	0
T50	5972	8	0	0
T79	0	10	0	0
T83	0	30	0	0
T87	0	12	0	0
T88	0	22	0	0
T90	0	1	0	0
T91	0	23	0	0