Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12304103	9300	0	0
alert_regwen_rd_A	12304103	4176	0	0
cpu_regwen_rd_A	12304103	4180	0	0
sw_rst_ctrl_n_0_rd_A	12304103	8579	0	0
sw_rst_ctrl_n_1_rd_A	12304103	8639	0	0
sw_rst_ctrl_n_2_rd_A	12304103	8287	0	0
sw_rst_ctrl_n_3_rd_A	12304103	8888	0	0
sw_rst_ctrl_n_4_rd_A	12304103	8590	0	0
sw_rst_ctrl_n_5_rd_A	12304103	8793	0	0
sw_rst_ctrl_n_6_rd_A	12304103	8917	0	0
sw_rst_ctrl_n_7_rd_A	12304103	8625	0	0
sw_rst_regwen_0_rd_A	12304103	4491	0	0
sw_rst_regwen_1_rd_A	12304103	4490	0	0
sw_rst_regwen_2_rd_A	12304103	4539	0	0
sw_rst_regwen_3_rd_A	12304103	4631	0	0
sw_rst_regwen_4_rd_A	12304103	4688	0	0
sw_rst_regwen_5_rd_A	12304103	4734	0	0
sw_rst_regwen_6_rd_A	12304103	4672	0	0
sw_rst_regwen_7_rd_A	12304103	4860	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	9300	0	0
T69	4610	24	0	0
T70	2627	49	0	0
T71	11432	2	0	0
T72	11315	392	0	0
T73	16387	1	0	0
T92	3154	18	0	0
T93	3831	16	0	0
T94	3299	19	0	0
T97	3289	11	0	0
T98	11178	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	4176	0	0
T7	48623	49	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T26	5100	0	0	0
T50	5881	0	0	0
T65	0	147	0	0
T88	0	154	0	0
T90	0	90	0	0
T91	0	119	0	0
T103	0	34	0	0
T123	0	135	0	0
T124	0	209	0	0
T125	0	344	0	0
T126	0	84	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	4180	0	0
T7	48623	35	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T26	5100	0	0	0
T50	5881	0	0	0
T65	0	147	0	0
T88	0	183	0	0
T90	0	130	0	0
T91	0	192	0	0
T103	0	46	0	0
T123	0	130	0	0
T124	0	216	0	0
T125	0	336	0	0
T126	0	52	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	8579	0	0
T7	48623	161	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	9	0	0
T14	23382	0	0	0
T15	0	9	0	0
T26	5100	0	0	0
T37	0	111	0	0
T38	0	7	0	0
T50	5881	0	0	0
T86	0	13	0	0
T88	0	339	0	0
T90	0	95	0	0
T91	0	323	0	0
T103	0	48	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	8639	0	0
T7	48623	146	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T15	0	3	0	0
T26	5100	0	0	0
T37	0	135	0	0
T38	0	6	0	0
T50	5881	0	0	0
T79	0	113	0	0
T86	0	20	0	0
T88	0	396	0	0
T90	0	105	0	0
T91	0	281	0	0
T103	0	41	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	8287	0	0
T7	48623	143	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	3	0	0
T14	23382	0	0	0
T15	0	10	0	0
T26	5100	0	0	0
T37	0	95	0	0
T38	0	5	0	0
T50	5881	0	0	0
T86	0	17	0	0
T88	0	318	0	0
T90	0	153	0	0
T91	0	338	0	0
T103	0	35	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	8888	0	0
T7	48623	141	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	10	0	0
T14	23382	0	0	0
T15	0	6	0	0
T26	5100	0	0	0
T37	0	147	0	0
T38	0	3	0	0
T50	5881	0	0	0
T86	0	16	0	0
T88	0	372	0	0
T90	0	143	0	0
T91	0	326	0	0
T103	0	41	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	8590	0	0
T7	48623	132	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	3	0	0
T14	23382	0	0	0
T15	0	11	0	0
T26	5100	0	0	0
T37	0	134	0	0
T38	0	11	0	0
T50	5881	0	0	0
T86	0	16	0	0
T88	0	330	0	0
T90	0	125	0	0
T91	0	390	0	0
T103	0	46	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	8793	0	0
T7	48623	147	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	1	0	0
T14	23382	0	0	0
T15	0	9	0	0
T26	5100	0	0	0
T37	0	114	0	0
T38	0	7	0	0
T50	5881	0	0	0
T86	0	19	0	0
T88	0	336	0	0
T90	0	119	0	0
T91	0	326	0	0
T103	0	45	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	8917	0	0
T7	48623	188	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T15	0	10	0	0
T26	5100	0	0	0
T37	0	141	0	0
T38	0	9	0	0
T50	5881	0	0	0
T79	0	75	0	0
T86	0	13	0	0
T88	0	348	0	0
T90	0	137	0	0
T91	0	349	0	0
T103	0	58	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	8625	0	0
T7	48623	171	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	8	0	0
T14	23382	0	0	0
T15	0	4	0	0
T26	5100	0	0	0
T37	0	124	0	0
T38	0	4	0	0
T50	5881	0	0	0
T86	0	11	0	0
T88	0	331	0	0
T90	0	153	0	0
T91	0	310	0	0
T103	0	45	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	4491	0	0
T7	48623	50	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T26	5100	0	0	0
T37	0	2	0	0
T50	5881	0	0	0
T65	0	159	0	0
T79	0	7	0	0
T82	0	8	0	0
T86	0	6	0	0
T88	0	203	0	0
T90	0	94	0	0
T91	0	196	0	0
T103	0	40	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	4490	0	0
T7	48623	38	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T26	5100	0	0	0
T37	0	17	0	0
T50	5881	0	0	0
T65	0	179	0	0
T79	0	25	0	0
T86	0	7	0	0
T88	0	197	0	0
T90	0	81	0	0
T91	0	136	0	0
T103	0	40	0	0
T127	0	18	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	4539	0	0
T7	48623	56	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T26	5100	0	0	0
T37	0	26	0	0
T50	5881	0	0	0
T65	0	178	0	0
T79	0	24	0	0
T82	0	10	0	0
T86	0	3	0	0
T88	0	146	0	0
T90	0	114	0	0
T91	0	144	0	0
T103	0	54	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	4631	0	0
T7	48623	57	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T26	5100	0	0	0
T37	0	11	0	0
T50	5881	0	0	0
T65	0	151	0	0
T79	0	19	0	0
T82	0	7	0	0
T86	0	5	0	0
T88	0	196	0	0
T90	0	93	0	0
T91	0	141	0	0
T103	0	39	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	4688	0	0
T7	48623	54	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T26	5100	0	0	0
T37	0	17	0	0
T50	5881	0	0	0
T65	0	127	0	0
T79	0	22	0	0
T82	0	11	0	0
T86	0	12	0	0
T88	0	205	0	0
T90	0	111	0	0
T91	0	120	0	0
T103	0	50	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	4734	0	0
T7	48623	58	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T26	5100	0	0	0
T37	0	20	0	0
T50	5881	0	0	0
T65	0	154	0	0
T79	0	31	0	0
T82	0	5	0	0
T86	0	5	0	0
T88	0	173	0	0
T90	0	117	0	0
T91	0	157	0	0
T103	0	44	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	4672	0	0
T7	48623	44	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T26	5100	0	0	0
T37	0	3	0	0
T50	5881	0	0	0
T65	0	175	0	0
T79	0	18	0	0
T82	0	6	0	0
T86	0	7	0	0
T88	0	180	0	0
T90	0	128	0	0
T91	0	157	0	0
T103	0	51	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12304103	4860	0	0
T7	48623	65	0	0
T8	14110	0	0	0
T9	1521	0	0	0
T10	16381	0	0	0
T11	3661	0	0	0
T12	3228	0	0	0
T13	1729	0	0	0
T14	23382	0	0	0
T26	5100	0	0	0
T37	0	27	0	0
T50	5881	0	0	0
T65	0	138	0	0
T79	0	27	0	0
T82	0	5	0	0
T86	0	8	0	0
T88	0	162	0	0
T90	0	85	0	0
T91	0	150	0	0
T103	0	36	0	0