Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	593333	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

356775

1

T1

13

T3

435

T4

141

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	505124	1			T1	18		T2	10		T3	563
values[0x0]	221705	1			T1	7		T3	252		T4	90
values[0x1]	223279	1			T1	13		T3	265		T4	103

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	498122	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

451986

1

T1

17

T2

8

T3

529

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3373	1			T3	3		T9	12		T13	1
valid_sources[0x01]	3733	1			T3	7		T4	2		T8	1
valid_sources[0x02]	3107	1			T3	3		T4	2		T9	7
valid_sources[0x03]	3076	1			T3	7		T4	2		T8	2
valid_sources[0x04]	3854	1			T3	9		T4	2		T8	1
valid_sources[0x05]	4582	1			T3	3		T4	1		T9	13
valid_sources[0x06]	2961	1			T3	8		T8	4		T9	9
valid_sources[0x07]	6263	1			T3	2		T4	3		T8	2
valid_sources[0x08]	3364	1			T3	1		T4	2		T8	2
valid_sources[0x09]	3440	1			T3	1		T9	14		T41	8
valid_sources[0x0a]	3797	1			T3	3		T4	1		T7	85
valid_sources[0x0b]	3529	1			T3	2		T4	1		T8	1
valid_sources[0x0c]	4685	1			T3	4		T9	17		T11	2
valid_sources[0x0d]	3602	1			T3	5		T9	5		T11	1
valid_sources[0x0e]	3143	1			T3	5		T4	3		T9	10
valid_sources[0x0f]	3965	1			T3	2		T8	1		T9	13
valid_sources[0x10]	2946	1			T3	4		T4	1		T9	8
valid_sources[0x11]	3136	1			T3	3		T4	1		T8	4
valid_sources[0x12]	3234	1			T3	8		T8	2		T9	18
valid_sources[0x13]	2802	1			T3	3		T4	2		T8	1
valid_sources[0x14]	2961	1			T3	5		T4	1		T8	1
valid_sources[0x15]	2859	1			T3	2		T9	20		T11	1
valid_sources[0x16]	3143	1			T3	4		T4	1		T8	1
valid_sources[0x17]	3748	1			T3	4		T4	1		T9	15
valid_sources[0x18]	3149	1			T3	2		T4	1		T9	11
valid_sources[0x19]	3230	1			T3	3		T4	1		T8	3
valid_sources[0x1a]	3136	1			T3	7		T4	2		T8	1
valid_sources[0x1b]	4030	1			T3	4		T8	3		T9	28
valid_sources[0x1c]	3483	1			T3	6		T4	2		T8	1
valid_sources[0x1d]	3401	1			T3	6		T4	2		T8	2
valid_sources[0x1e]	2985	1			T3	4		T4	1		T8	1
valid_sources[0x1f]	2689	1			T3	4		T8	3		T9	9
valid_sources[0x20]	3598	1			T3	4		T4	3		T8	2
valid_sources[0x21]	4461	1			T3	4		T4	1		T8	1
valid_sources[0x22]	4297	1			T3	1		T9	7		T13	2
valid_sources[0x23]	2937	1			T3	4		T8	1		T9	13
valid_sources[0x24]	3103	1			T3	2		T9	8		T13	2
valid_sources[0x25]	3214	1			T3	6		T9	6		T11	2
valid_sources[0x26]	5056	1			T3	5		T4	2		T9	12
valid_sources[0x27]	4869	1			T3	4		T8	1		T9	5
valid_sources[0x28]	3142	1			T3	2		T4	1		T8	1
valid_sources[0x29]	3039	1			T3	2		T8	4		T9	8
valid_sources[0x2a]	3599	1			T3	3		T4	2		T9	15
valid_sources[0x2b]	4009	1			T3	6		T4	2		T9	18
valid_sources[0x2c]	3823	1			T3	3		T9	10		T11	2
valid_sources[0x2d]	3201	1			T3	6		T4	3		T8	1
valid_sources[0x2e]	3797	1			T3	4		T4	2		T8	1
valid_sources[0x2f]	3604	1			T3	4		T4	2		T8	1
valid_sources[0x30]	3474	1			T3	1		T9	8		T11	1
valid_sources[0x31]	3209	1			T3	4		T8	2		T9	5
valid_sources[0x32]	6247	1			T3	1		T8	2		T9	6
valid_sources[0x33]	3743	1			T3	5		T4	2		T8	2
valid_sources[0x34]	5082	1			T3	5		T4	1		T9	12
valid_sources[0x35]	3671	1			T3	1		T4	2		T9	9
valid_sources[0x36]	3480	1			T4	2		T8	1		T9	10
valid_sources[0x37]	3044	1			T3	2		T4	1		T9	8
valid_sources[0x38]	3419	1			T3	4		T4	2		T9	20
valid_sources[0x39]	6682	1			T3	7		T4	6		T8	1
valid_sources[0x3a]	3342	1			T3	6		T4	3		T9	14
valid_sources[0x3b]	4373	1			T3	4		T4	1		T8	1
valid_sources[0x3c]	3898	1			T3	3		T8	2		T9	16
valid_sources[0x3d]	3615	1			T3	3		T4	1		T8	1
valid_sources[0x3e]	5568	1			T3	3		T4	1		T8	1
valid_sources[0x3f]	4116	1			T3	6		T4	2		T8	1
valid_sources[0x40]	3698	1			T3	4		T8	1		T9	12
valid_sources[0x41]	3182	1			T3	5		T8	1		T9	6
valid_sources[0x42]	3135	1			T3	1		T9	15		T11	3
valid_sources[0x43]	2802	1			T3	2		T4	2		T8	2
valid_sources[0x44]	4310	1			T3	3		T4	6		T8	1
valid_sources[0x45]	3582	1			T3	2		T4	2		T8	1
valid_sources[0x46]	3186	1			T3	4		T8	3		T9	12
valid_sources[0x47]	3979	1			T3	1		T9	6		T13	3
valid_sources[0x48]	3824	1			T3	6		T9	17		T13	1
valid_sources[0x49]	2875	1			T3	6		T4	6		T9	6
valid_sources[0x4a]	2852	1			T3	6		T4	3		T8	1
valid_sources[0x4b]	3106	1			T3	5		T8	1		T9	24
valid_sources[0x4c]	5691	1			T3	3		T4	1		T9	4
valid_sources[0x4d]	3277	1			T3	6		T8	1		T9	16
valid_sources[0x4e]	4296	1			T3	5		T8	2		T9	10
valid_sources[0x4f]	3092	1			T3	4		T4	2		T8	2
valid_sources[0x50]	2623	1			T3	2		T4	1		T8	1
valid_sources[0x51]	3282	1			T3	7		T4	2		T8	1
valid_sources[0x52]	3113	1			T3	7		T8	2		T9	4
valid_sources[0x53]	3126	1			T3	3		T8	1		T9	11
valid_sources[0x54]	2902	1			T9	17		T11	1		T41	6
valid_sources[0x55]	3219	1			T3	7		T4	4		T8	1
valid_sources[0x56]	3287	1			T3	6		T4	5		T9	16
valid_sources[0x57]	4250	1			T3	4		T4	1		T8	1
valid_sources[0x58]	6954	1			T3	3		T8	3		T9	16
valid_sources[0x59]	3597	1			T3	1		T4	2		T8	2
valid_sources[0x5a]	3752	1			T3	1		T4	2		T9	7
valid_sources[0x5b]	3215	1			T3	2		T4	1		T8	1
valid_sources[0x5c]	2560	1			T3	3		T4	6		T9	16
valid_sources[0x5d]	3852	1			T3	6		T4	2		T9	13
valid_sources[0x5e]	4729	1			T3	2		T4	4		T8	1
valid_sources[0x5f]	2953	1			T3	3		T4	8		T9	7
valid_sources[0x60]	3495	1			T3	4		T4	5		T9	20
valid_sources[0x61]	4573	1			T3	4		T4	2		T9	9
valid_sources[0x62]	3344	1			T3	3		T4	2		T8	1
valid_sources[0x63]	4220	1			T3	6		T4	2		T9	10
valid_sources[0x64]	3039	1			T3	3		T4	1		T8	3
valid_sources[0x65]	3341	1			T3	2		T9	16		T11	2
valid_sources[0x66]	3173	1			T3	4		T4	2		T8	4
valid_sources[0x67]	6268	1			T3	4		T4	1		T9	9
valid_sources[0x68]	4368	1			T3	7		T9	17		T13	1
valid_sources[0x69]	3601	1			T3	2		T8	2		T9	15
valid_sources[0x6a]	3847	1			T3	6		T4	1		T9	14
valid_sources[0x6b]	4559	1			T3	7		T4	1		T8	1
valid_sources[0x6c]	3115	1			T3	3		T9	11		T12	3
valid_sources[0x6d]	3774	1			T3	6		T4	2		T9	10
valid_sources[0x6e]	2728	1			T3	8		T8	1		T9	16
valid_sources[0x6f]	3810	1			T3	6		T8	2		T9	10
valid_sources[0x70]	2921	1			T3	7		T9	8		T11	2
valid_sources[0x71]	3041	1			T3	4		T4	3		T8	1
valid_sources[0x72]	2860	1			T3	1		T4	1		T8	1
valid_sources[0x73]	3535	1			T3	5		T4	1		T9	30
valid_sources[0x74]	4092	1			T3	6		T4	5		T8	1
valid_sources[0x75]	3394	1			T3	5		T8	2		T9	7
valid_sources[0x76]	3836	1			T3	8		T4	7		T9	9
valid_sources[0x77]	3289	1			T3	4		T4	1		T8	2
valid_sources[0x78]	3506	1			T3	5		T4	1		T8	1
valid_sources[0x79]	3704	1			T3	5		T4	4		T8	2
valid_sources[0x7a]	3252	1			T3	1		T9	14		T12	6
valid_sources[0x7b]	2758	1			T3	4		T8	1		T9	6
valid_sources[0x7c]	2942	1			T3	6		T4	3		T8	2
valid_sources[0x7d]	3544	1			T3	4		T4	1		T9	8
valid_sources[0x7e]	3410	1			T3	5		T4	2		T8	3
valid_sources[0x7f]	3898	1			T3	4		T4	1		T8	2
valid_sources[0x80]	5560	1			T3	1		T4	1		T9	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

237430

1

T1

10

T3

305

T4

90

values[0x0]

all_enables

biggest_size

77724

1

T1

3

T3

88

T4

29

values[0x1]

all_enables

biggest_size

41621

1

T3

42

T4

22

T5

1