Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T13
0	1	Covered	T13,T44,T58
1	0	Covered	T4,T44,T58

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T4,T11,T13
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52526203	8347	0	0
CascadeEffAonToRstPorAboveRise_A	52526203	8347	0	0
CascadeEffAonToRstPorIoAboveFall_A	50423670	8347	0	0
CascadeEffAonToRstPorIoAboveRise_A	50423670	8347	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25212584	8347	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25212584	8347	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12606006	8347	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12606006	8347	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25212631	8347	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25212631	8347	0	0
CascadeLcToLcAboveFall_A	52526203	20963	0	0
CascadeLcToLcAboveRise_A	52526203	20963	0	0
CascadeLcToLcAonAboveFall_A	1591472	20963	0	0
CascadeLcToLcAonAboveRise_A	1591472	20963	0	0
CascadeLcToLcShadowedAboveFall_A	52526203	20963	0	0
CascadeLcToLcShadowedAboveRise_A	52526203	20963	0	0
CascadePorToAonAboveFall_A	1591472	6755	0	0
CascadeSysToSysAboveFall_A	52526203	20963	0	0
CascadeSysToSysAboveRise_A	52526203	20963	0	0
ScanRstToAonRise_A	1591472	182	0	0
StablePorToAonRise_A	1591472	8347	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11236847	20963	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11236847	20963	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11236847	20963	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11236847	20963	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12606006	20963	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12606006	20963	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11236847	20963	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11236847	20963	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11236847	20963	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11236847	20963	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52526203	8347	0	0
T1	9313	1	0	0
T2	833732	271	0	0
T3	53318	1	0	0
T4	19287	2	0	0
T5	6342	1	0	0
T6	24241	8	0	0
T7	7693	1	0	0
T8	17512	1	0	0
T9	187012	27	0	0
T10	121185	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52526203	8347	0	0
T1	9313	1	0	0
T2	833732	271	0	0
T3	53318	1	0	0
T4	19287	2	0	0
T5	6342	1	0	0
T6	24241	8	0	0
T7	7693	1	0	0
T8	17512	1	0	0
T9	187012	27	0	0
T10	121185	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50423670	8347	0	0
T1	8940	1	0	0
T2	800402	271	0	0
T3	51183	1	0	0
T4	18515	2	0	0
T5	6089	1	0	0
T6	23283	8	0	0
T7	7386	1	0	0
T8	16810	1	0	0
T9	179555	27	0	0
T10	116355	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50423670	8347	0	0
T1	8940	1	0	0
T2	800402	271	0	0
T3	51183	1	0	0
T4	18515	2	0	0
T5	6089	1	0	0
T6	23283	8	0	0
T7	7386	1	0	0
T8	16810	1	0	0
T9	179555	27	0	0
T10	116355	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212584	8347	0	0
T1	4469	1	0	0
T2	400235	271	0	0
T3	25591	1	0	0
T4	9257	2	0	0
T5	3043	1	0	0
T6	11643	8	0	0
T7	3693	1	0	0
T8	8405	1	0	0
T9	89767	27	0	0
T10	58161	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212584	8347	0	0
T1	4469	1	0	0
T2	400235	271	0	0
T3	25591	1	0	0
T4	9257	2	0	0
T5	3043	1	0	0
T6	11643	8	0	0
T7	3693	1	0	0
T8	8405	1	0	0
T9	89767	27	0	0
T10	58161	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	8347	0	0
T1	2233	1	0	0
T2	200065	271	0	0
T3	12795	1	0	0
T4	4628	2	0	0
T5	1520	1	0	0
T6	5815	8	0	0
T7	1846	1	0	0
T8	4201	1	0	0
T9	44883	27	0	0
T10	29085	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	8347	0	0
T1	2233	1	0	0
T2	200065	271	0	0
T3	12795	1	0	0
T4	4628	2	0	0
T5	1520	1	0	0
T6	5815	8	0	0
T7	1846	1	0	0
T8	4201	1	0	0
T9	44883	27	0	0
T10	29085	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212631	8347	0	0
T1	4469	1	0	0
T2	400249	271	0	0
T3	25592	1	0	0
T4	9258	2	0	0
T5	3043	1	0	0
T6	11643	8	0	0
T7	3693	1	0	0
T8	8406	1	0	0
T9	89778	27	0	0
T10	58161	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212631	8347	0	0
T1	4469	1	0	0
T2	400249	271	0	0
T3	25592	1	0	0
T4	9258	2	0	0
T5	3043	1	0	0
T6	11643	8	0	0
T7	3693	1	0	0
T8	8406	1	0	0
T9	89778	27	0	0
T10	58161	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52526203	20963	0	0
T1	9313	3	0	0
T2	833732	271	0	0
T3	53318	1	0	0
T4	19287	6	0	0
T5	6342	1	0	0
T6	24241	8	0	0
T7	7693	5	0	0
T8	17512	14	0	0
T9	187012	102	0	0
T10	121185	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52526203	20963	0	0
T1	9313	3	0	0
T2	833732	271	0	0
T3	53318	1	0	0
T4	19287	6	0	0
T5	6342	1	0	0
T6	24241	8	0	0
T7	7693	5	0	0
T8	17512	14	0	0
T9	187012	102	0	0
T10	121185	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591472	20963	0	0
T1	278	3	0	0
T2	25136	271	0	0
T3	1598	1	0	0
T4	578	6	0	0
T5	188	1	0	0
T6	729	8	0	0
T7	230	5	0	0
T8	523	14	0	0
T9	5624	102	0	0
T10	3650	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591472	20963	0	0
T1	278	3	0	0
T2	25136	271	0	0
T3	1598	1	0	0
T4	578	6	0	0
T5	188	1	0	0
T6	729	8	0	0
T7	230	5	0	0
T8	523	14	0	0
T9	5624	102	0	0
T10	3650	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52526203	20963	0	0
T1	9313	3	0	0
T2	833732	271	0	0
T3	53318	1	0	0
T4	19287	6	0	0
T5	6342	1	0	0
T6	24241	8	0	0
T7	7693	5	0	0
T8	17512	14	0	0
T9	187012	102	0	0
T10	121185	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52526203	20963	0	0
T1	9313	3	0	0
T2	833732	271	0	0
T3	53318	1	0	0
T4	19287	6	0	0
T5	6342	1	0	0
T6	24241	8	0	0
T7	7693	5	0	0
T8	17512	14	0	0
T9	187012	102	0	0
T10	121185	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591472	6755	0	0
T1	278	1	0	0
T2	25136	271	0	0
T3	1598	1	0	0
T4	578	1	0	0
T5	188	1	0	0
T6	729	8	0	0
T7	230	1	0	0
T8	523	1	0	0
T9	5624	27	0	0
T10	3650	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52526203	20963	0	0
T1	9313	3	0	0
T2	833732	271	0	0
T3	53318	1	0	0
T4	19287	6	0	0
T5	6342	1	0	0
T6	24241	8	0	0
T7	7693	5	0	0
T8	17512	14	0	0
T9	187012	102	0	0
T10	121185	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52526203	20963	0	0
T1	9313	3	0	0
T2	833732	271	0	0
T3	53318	1	0	0
T4	19287	6	0	0
T5	6342	1	0	0
T6	24241	8	0	0
T7	7693	5	0	0
T8	17512	14	0	0
T9	187012	102	0	0
T10	121185	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591472	182	0	0
T30	0	3	0	0
T34	7103	0	0	0
T44	16918	2	0	0
T45	5619	0	0	0
T50	530	0	0	0
T51	366	0	0	0
T52	731	0	0	0
T53	1306	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	20081	3	0	0
T59	14649	2	0	0
T63	394	0	0	0
T94	0	2	0	0
T95	0	2	0	0
T101	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591472	8347	0	0
T1	278	1	0	0
T2	25136	271	0	0
T3	1598	1	0	0
T4	578	2	0	0
T5	188	1	0	0
T6	729	8	0	0
T7	230	1	0	0
T8	523	1	0	0
T9	5624	27	0	0
T10	3650	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11236847	20963	0	0
T1	1943	3	0	0
T2	194594	271	0	0
T3	12705	1	0	0
T4	4339	6	0	0
T5	1478	1	0	0
T6	5466	8	0	0
T7	1517	5	0	0
T8	3302	14	0	0
T9	42238	102	0	0
T10	26118	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11236847	20963	0	0
T1	1943	3	0	0
T2	194594	271	0	0
T3	12705	1	0	0
T4	4339	6	0	0
T5	1478	1	0	0
T6	5466	8	0	0
T7	1517	5	0	0
T8	3302	14	0	0
T9	42238	102	0	0
T10	26118	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11236847	20963	0	0
T1	1943	3	0	0
T2	194594	271	0	0
T3	12705	1	0	0
T4	4339	6	0	0
T5	1478	1	0	0
T6	5466	8	0	0
T7	1517	5	0	0
T8	3302	14	0	0
T9	42238	102	0	0
T10	26118	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11236847	20963	0	0
T1	1943	3	0	0
T2	194594	271	0	0
T3	12705	1	0	0
T4	4339	6	0	0
T5	1478	1	0	0
T6	5466	8	0	0
T7	1517	5	0	0
T8	3302	14	0	0
T9	42238	102	0	0
T10	26118	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	20963	0	0
T1	2233	3	0	0
T2	200065	271	0	0
T3	12795	1	0	0
T4	4628	6	0	0
T5	1520	1	0	0
T6	5815	8	0	0
T7	1846	5	0	0
T8	4201	14	0	0
T9	44883	102	0	0
T10	29085	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	20963	0	0
T1	2233	3	0	0
T2	200065	271	0	0
T3	12795	1	0	0
T4	4628	6	0	0
T5	1520	1	0	0
T6	5815	8	0	0
T7	1846	5	0	0
T8	4201	14	0	0
T9	44883	102	0	0
T10	29085	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11236847	20963	0	0
T1	1943	3	0	0
T2	194594	271	0	0
T3	12705	1	0	0
T4	4339	6	0	0
T5	1478	1	0	0
T6	5466	8	0	0
T7	1517	5	0	0
T8	3302	14	0	0
T9	42238	102	0	0
T10	26118	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11236847	20963	0	0
T1	1943	3	0	0
T2	194594	271	0	0
T3	12705	1	0	0
T4	4339	6	0	0
T5	1478	1	0	0
T6	5466	8	0	0
T7	1517	5	0	0
T8	3302	14	0	0
T9	42238	102	0	0
T10	26118	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11236847	20963	0	0
T1	1943	3	0	0
T2	194594	271	0	0
T3	12705	1	0	0
T4	4339	6	0	0
T5	1478	1	0	0
T6	5466	8	0	0
T7	1517	5	0	0
T8	3302	14	0	0
T9	42238	102	0	0
T10	26118	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11236847	20963	0	0
T1	1943	3	0	0
T2	194594	271	0	0
T3	12705	1	0	0
T4	4339	6	0	0
T5	1478	1	0	0
T6	5466	8	0	0
T7	1517	5	0	0
T8	3302	14	0	0
T9	42238	102	0	0
T10	26118	102	0	0